Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-Layered Stacked-Chip Packaging

Abstract

Abstract To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is a three-dimensional integrated circuit (3D-IC) package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of microsolder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg microsolder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis (FEA) is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg microsolder joint can be achieved at 10 μm of each chip thickness, 230 μm and 5 μm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermomechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.