Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures

Abstract

As the market demands for high performance, miniaturized, better reliability and lower-priced portable electronic products, the integration of a system into three-dimensional (3D) chip stacking packages are presently used to achieve these targets. Even though the miniaturization of system scaling, low power consumption and better electrical performance can be performed by 3DIC packaging technologies, thermo-mechanical problems occur due to the 3D stacking feature. Because dice are vertically stacked in 3DIC packages, higher junction temperature as well as temperature concentration phenomenon inside the stacking dice are resulted in and cause larger corresponding thermal induced stresses. Hence, the problems of heat dissipation and thermal induced stresses always cause failures or fatigues in 3D stacked IC packages and become critical reliability issues. In order to realize thermo-mechanical coupling effects in 3D vertical stacked IC packages with spacer structures, four layer vertical stacked dice (bare die to bare die) with TSV (through-silicon-via), metal bumps, and spacer structures are constructed as the test vehicle. In the thermo-mechanical coupling simulative study, the accurate convection heat transfer coefficients that obtained from computational fluid dynamics technique are used as the applied boundary conditions in finite element analysis (FEA) modeling to obtain precisely thermal stress distributions. Therefore, not only the temperature distributions and thermal characteristics (thermal resistance and junction temperature) can be resolved but also the corresponding precisely thermal stress distributions can be illustrated by using FEA. These results can be most effectively used as design guidelines to engineers if thermo-mechanical coupling solutions for 3D vertical stacked IC package with the conditions of dice powered on are required.