Reliability analysis of 3D IC integration packaging under drop test condition

Abstract

Consumer electronic products are evolving toward smaller size and higher efficiency. 3D IC packaging has smaller form factor and lower signal delay compared with conventional packaging. Thus, it has been widely used in mobile electronic devices. Mobile electronic device is prone to being dropped during operation. Hence, the drop reliability of electronic packaging is an important issue in 3D ICs. Numerous 3D IC packaging issues, such as fabrication process, structure design, and thermal cycling reliability have been studied. However, few studies focus on 3D packaging drop reliability assessment. Conventionally, board level drop test is widely used in determining the drop reliability of electronic packaging. In this study, 3D IC packaging structure is established by using the finite element (FE) analysis software ANSYS/LS-DYNA 3D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> . The simulation result is validated by using the board level drop test. The dynamic behavior of 3D IC packaging during board level drop test was observed. Parametric study was also performed to study the effect of structure size and material. Unlike under thermal cycling test condition, increasing chip stacking number may reduce the reliability of copper bumps under drop test condition. Moreover, adding underfill between interposer and test board can enhance solder ball reliability. However, copper bump reliability is reduced, as the interposer under certain thickness.