FEA modeling and DOE analysis for design optimization of 3D-WLP

Abstract

With the rapid development of IC technologies, topics of 3D stacked IC packages are now being studied vastly around the world. In 3D stacked IC technologies, many electrical characteristics have been proved to have great improvements, but their corresponding thermo-mechanical problems are raising as well. Due to the reason of ICs stacking, thermo-mechanical problems are becoming more serious than those in traditional single IC package. These problems include the heat dissipation, die breaking, interfacial delamination, via cracking and so on. These corresponding problems not only cause failures in 3D stacked IC packages but also have significant influences on reliability. For the sake of realizing critical stress distributions in 3D stacked IC packages, the three dimensional finite element analysis (FEA) modeling has been employed in this paper. The 3D-WLP (wafer-level-package) with ten layer chips stacking is selected as our test vehicle. By using three dimensional FEA modeling, thermal induced stress distributions in 3D-WLP when subjected to a uniform temperature change can be illustrated. Further, the design of experiments (DOE) analysis for design optimization has also been used to obtain the sensitivities of geometry and material properties of 3D-WLP. Several geometric dimensions and material properties are selected as main design factors and the average value of maximum von Mises stress in copper vias and chips is chosen as the response to be optimized. Through the DOE analysis, the optimum geometry and material properties of 3D-WLP and this result in smaller von Mises stresses in copper via and chip configurations can be obtained. These results can be most effectively used as design guidelines to engineers when optimum stress solutions in 3D-WLP are required.