DOE Analysis of Effects of Geometry and Materials on Cu/Low-K Interconnect Stresses

Abstract

In 3D-IC packages, the low-k dielectrics are favored to improve many electrical characteristics in IC devices; hence the corresponding researches are being widely studied extensively. For the purpose of studying thermal-mechanical effects on Cu/low-k interconnects in the wafer, the three dimensional finite element analysis (FEA) was adopted in this paper. Several low-k dielectrics were considered in FEA, which are SiLK, BCB and SiCOH. By using FEA, the corresponding thermal-mechanical induced stresses distribution of Cu/low-k interconnects would be obtained. Furthermore, in order to study the sensitivity information of Cu/low-k interconnects, the method of design of experiments (DOE) as well as factorial design methodology and response surface methodology were also used. Five major parameters of geometric dimensions of copper interconnects/vias structure were selected as the design factors and the maximum average value of von Mises stress in copper interconnects/vias structure was selected as the response to be optimized. Through the DOE analysis, the optimum geometric parameters of copper interconnects/vias structure that resulted in smaller von Mises stresses in Cu/low-k interconnects could be obtained. The results also show that the geometric dimension of copper interconnects/vias had significant influence on von Mises stresses distribution. Moreover, the maximum value of von Mises stress for different copper interconnects/vias geometric dimensions could also be easily predicted by using the response surface curve and its corresponding regression model from DOE analysis.