Intrinsic Stress Effect of Fabricated Processes on the Warpage and Microbump Reliability of Thin-Type 3D-ICs Packaging

Abstract

Owing to the fact that the requirements of the lifestyle for electronics devices has been shifted to a stage physically small and thin, a high density of chips is designed to meet the foregoing demands under the limited space. Although in plane IC packaging technology has been maturely developed, it has encountered a bottleneck which stops it from immediate progress. Therefore, it is inevitable that the 3DICs packaging becomes the major goal of technological developments in the future. Among them, through silicon via (TSV) is one of the critical techniques. Because of the complexity in the design of 3D-ICs, the interaction among packaging components is expected to affect the reliability. Consequently, this research presents the 3D-ICs packaging with two ultra-thin chip stackings to examine their mechanical reliability of TSV and SnAg microjoints under only the thermal cycling test and the accompanied effect of process-dependent thermal loading simulation combined with the introduction of temperature cycling loads. Several concerned parameters of the above-mentioned packaging framework, such as the chip thickness, TSV pitch, and TSV radius, are parametrically discussed by finite element analysis while the filled underfill materials with different Young’s modulus are taken into account, separately. The analytic results show that when the double-layered chip stacking packaging structure is applied by the thermal cycling period, a better fatigue life of SnAg microjoints could be obtained under the situation of either the thinner chip, the longer TSV pitch, or the smaller TSV radius. Finally, through the analytic assistance of a full factorial design, the geometrical effects of double-layered chip stacking packaging are performed parametrically investigations.