Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

Abstract

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.