3-D TSV Six-Die Stacking and Reliability Assessment of 20- $\mu$ m-Pitch Bumps on Large-Scale Dies

Abstract

3-D integration typically involves multiple chips stacking with large numbers of interconnections within each chip. There are several fundamental technology challenges that need to be addressed in order to realize 3-D integration, such as Cu through-silicon via (TSV) expansion, transistor degradation or open failures on Cu contamination, microbump stress, and so on. The reliability issues on TSV and microbumps are very critical not only for a stacked chip package, but also during wafer-level processes. In this paper, the authors successfully stacked six chips with a thickness of 50 $\mu \text{m}$ and assessed their reliability. Each chip consists of 122054 bumps with a bump diameter of $10~\mu \text{m}$ and a pitch of 20 $\mu \text{m}$ . These bumps were built directly on TSVs, which have a diameter of $5~\mu \text{m}$ . Measured electrical resistance is well matched with calculated electrical resistance. Finally, this paper presents the reliability results of the 3-D IC packages that are embedded in molding compound.