Effects of post-CMP annealing on TSV Cu protrusion and leakage current

Abstract

Cu protrusion is a widely known challenge in through silicon via (TSV) fabrication which occurs because of the large mismatch in the coefficient of thermal expansion (CTE) between Cu and silicon. The leakage current of TSVs is the major electrical characteristic related to reliability of TSV. In this paper, Cu protrusion reliability was analyzed by Thermal Cycling (TC) test. A testing vehicle for linkage current was designed to evaluate the effects of annealing on the electrical property of TSV. Different post-CMP annealing processes were carried out to study the effects of the annealing parameters (annealing temperature and annealing time) on TSV Cu protrusion and leakage current. The TSV wafers were tested at different temperatures for 20 min, 200 °C, 300 °C, 400 °C, 500 °C, respectively and tested for different time at 400 °C, 20 min, 60 min, 120 min, 180 min, respectively. The TSV wafers without annealing were also evaluated as reference. The results showed that the Cu protrusion during annealing increased with the increasing of the annealing temperature and the annealing time. According to the TC test, the post-CMP annealing is of great importance to Cu protrusion reliability of TSV which could be improved with the high annealing temperature and the long annealing time. However, the leakage current increased with the increasing of the annealing temperature and the annealing time. It can be concluded that the optimal annealing process would be 60 min at 400 °C.