Metal contamination evaluation of a TSV reveal process using direct Si/Cu grinding and residual metal removal

Abstract

We evaluated the metal contamination generated by a through silicon via (TSV) reveal process using direct Si/Cu grinding and residual metal removal. To evaluate the metal contamination, a complementary metal oxide semiconductor (CMOS) + TSV wafer was prepared. The diameter and depth of the TSVs were 20 µm and 50 µm, respectively. TSV density was approximately 10%. The distance between each circuit component and TSV was 60 µm. After it was bonded to a glass support substrate, a TSV reveal process was performed by using direct Si/Cu grinding and residual metal removal. The wafer thickness after the TSV reveal process was 38 µm. After the TSV reveal process, the leakage current of the n+/p diodes and the capacitance-time characteristics of the n-type MOS capacitors were measured. The leakage current of the n+/p diodes was virtually unchanged after the TSV reveal process. In addition, the change in the generation lifetime of minority carriers determined by Zerbst analysis was less than 6%. These results demonstrate that the influence of the TSV reveal process on circuit components is small.