Abstract
We investigated metal contamination induced by a through silicon via (TSV) reveal process using direct Si/Cu grinding and residual metal removal. A complementary metal oxide semiconductor (CMOS) wafer including TSVs was bonded to a glass support substrate, and a TSV reveal process was performed by direct Si/Cu grinding and residual metal removal. Then, metal contamination near the SiO2/Si interface on the front side of the wafer was investigated by using a pulsed-MOS capacitor technique and measuring the effective generation lifetime and effective surface generation velocity before and after this TSV reveal process. The results of Zerbst analysis showed that the changes in average effective generation lifetime and average effective surface generation velocity were −5.4 and +4.2%, respectively. These results demonstrate that the effect of metal contamination induced by our TSV reveal process on circuit components is small.
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