Imperfection in TSV Modeling

Abstract

Through silicon via (TSV) is an emerging technology that enables vertical integration of silicon dies forming a single three-dimensional integrated circuit (3D-IC) stack. This chapter studies the capacitive coupling between TSVs and metal wires with wave simulation. The wave-simulation results show that coupling is not negligible when TSV is relatively short compared to the TSV width, where the aspect ratio is 5, the effect of metal wires is not considered. Moreover, the effect of metal lines on TSV–TSV coupling can be neglected if the pitch is less than three times the TSV diameter. Moreover, coupling between TSVs and complementary metal-oxide semiconductor (CMOS) transistors is investigated. Several isolation techniques are also introduced.