Residual stress effect of copper-filled through silicon via on performances of nano-scaled devices in 3D-ICs interposer

Abstract

The through-silicon via (TSV) technology is widely used in 3D-IC packaging today. After the TSV structure be manufactured, residual tensile stress is occurred in TSV and pull the silicon interposer seriously. Metal-oxide-semiconductor field-effect transistor (MOSFET) around the TSV is affect by pull situation, the mobility of MOSFET is changed. In this study, the influence of TSV residual stress is been discussion; moreover lattice-mismatch strained engineering is added to analysis with TSV residual stress. In strained engineering, SiGe alloys are implanted in drain and source. The characteristic of SiGe lattice mismatch is used to improve the mobility of P-type MOSFET. Finite element analysis is used to simulate the stress distribution of pMOSFET when pMOSFET is impacted by TSV residual stress and strained engineering. However, the geometry of TSV and pMOSFET having a great difference, so the simulation model of TSV and pMOSFET are created respectively. Global-Local technology is used to connect the models of TSV and MOSFET. Changing TSV diameter, TSV residual stress magnitude and pMOSFET gate width is used to observe deformation of average stress in each direction. Piezoresistive equation is used to calculate the mobility gain of pMOSFET. From the simulation results, the increase of TSV residual stress has reduced the mobility gain of pMOSFET. Using strain engineering techniques can increase the mobility of pMOSFET obviously, the maximum mobility gain is estimated to be 100% at simulation result. In this study, TSV residual stress and strain engineering can be confirmed that they have ability to influence the mobility of pMOSFET.