Through Silicon Via (TSV) redundancy - a high reliability, networking product perspective

Abstract

3-D, stacked ICs offer a promising solution to speed, power and density requirements, as the industry strives to scale to Moore's Law. Through Silicon Vias (TSV) are integral parts to 3-D stacked ICs. TSVs shorten interconnects between logic elements, thus reducing power while increasing performance. TSVs may comprise a significant portion (both logically and physically) of the 3D die stack. It's likely that tens of thousands of TSVs will be incorporated into a 3D die stack. Even though it's widely considered that the TSV yield will be very high, the large number of TSVs still presents a significant risk, given that it is difficult to have 100% test coverage, and a single TSV failure in the field can invalidate an entire die stack (multiplying yield loss by the number of die in the stack). Reliability of TSVs is not clearly understood yet and can also present significant field issues. TSV redundancy has been proposed as a way to mitigate the risk of TSV failure in the stack. This paper will look at published work on TSV redundancy, as well as standards and practical work. The paper will take a practical perspective, taking into account: cost, design (performance), and implementation/deployment considerations. The paper will conclude by providing guidelines and recommendations, which can be used to develop a TSV redundancy strategy at the device level for high reliability networking applications.