Threshold Voltage Stability Research Articles

A general approach for hysteresis-free, operationally stable metal halide perovskite field-effect transistors.

Despite sustained research, application of lead halide perovskites in field-effect transistors (FETs) has substantial concerns in terms of operational instabilities and hysteresis effects which are linked to its ionic nature. Here, we investigate the mechanism behind these instabilities and demonstrate an effective route to suppress them to realize high-performance perovskite FETs with low hysteresis, high threshold voltage stability (ΔVt < 2 V over 10 hours of continuous operation), and high mobility values >1 cm2/V·s at room temperature. We show that multiple cation incorporation using strain-relieving cations like Cs and cations such as Rb, which act as passivation/crystallization modifying agents, is an effective strategy for reducing vacancy concentration and ion migration in perovskite FETs. Furthermore, we demonstrate that treatment of perovskite films with positive azeotrope solvents that act as Lewis bases (acids) enables a further reduction in defect density and substantial improvement in performance and stability of n-type (p-type) perovskite devices.

A 1 MHz PVT compensated RC oscillator with $$\hbox {8 ppm}/^{\circ }\hbox {C}$$ frequency stability

This paper presents a 1 MHz PVT compensated dual phase relaxation Oscillator. The oscillator core employs a current controlled voltage bias replica circuit to limit the charging of capacitor. Furthermore, the current starved schmitt trigger circuit is employed in oscillator in place of conventional power consuming comparators. They also provide stable switching threshold voltage across temperature variations. The oscillator is designed in 90 nm STMicroelectronics BCD technology and validated to work for supply variations of 1.0–1.32 V and temperature range from − 40 to 175 °C to suitable for automotive, industrial as well as consumer applications.

Modelling of fin width dependent threshold voltage in fin shaped nano channel AlGaN/GaN HEMT

Abstract A systematic theoretical model of threshold voltage (VT) for AlGaN/GaN fin shaped nano channel HEMT (FinHEMT) structure has been proposed. This device can achieve enhancement mode operation with decreased fin width (Wfin). This proposed model captures the decreased two dimensional electron gas (2DEG) density due to combined effect of built-in partial strain relaxation and partial side wall depletion (Wdepl) of nano channel due to surface potential of sidewalls. This leads to positive VT which varies inversely with Wfin. This influence indicates that narrower fin width below 60 nm contributes to a stable positive threshold voltage.

Hole-Induced Degradation in ${E}$ -Mode GaN MIS-FETs: Impact of Substrate Terminations

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high ${V}_{\text {DS}}$ ) on the ${E}$ -mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage ( ${V}_{\text {TH}}$ ) stability than that with a grounded substrate. A non monotonic dependence of ${V}_{\text {TH}}$ shifts and OFF-state time-to-breakdown ( ${t}_{\text {BD}}$ ) on the positive substrate bias ( ${V}_{\text {sub}}$ ) was also observed. The underlying mechanisms are the different impacts of positive ${V}_{\text {sub}}$ on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good ${V}_{\text {TH}}$ stability in applications of the GaN MIS-FET.

Characterization of Static and Dynamic Behavior of 1200 V Normally off GaN/SiC Cascode Devices

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p -GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on -resistance ( R ON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage ( V TH), and no dynamic R ON degradation. To identify its safe operation in the off -state with a high drain bias, the off -state middle point voltage ( V M) between the E-mode device drain and D-mode device source is investigated. A relatively low off -state V M is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic V TH shift; and 2) suppress the increased dynamic off -state leakage current ( I OFF) induced by on -state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn- on and 121 V/ns during turn- off is achieved.

Suppression of Interfacial Disorders in Solution-Processed Metal Oxide Thin-Film Transistors by Mg Doping.

The fabrication of high-performance metal oxide thin-film transistors (TFTs) using a low-temperature solution process may facilitate the realization of ultraflexible and wearable electronic devices. However, the development of highly stable oxide gate dielectrics at a low temperature has been a challenging issue since a considerable amount of residual impurities and defective bonding states is present in low-temperature-processed gate dielectrics causing a large counterclockwise hysteresis and a significant instability. Here, we report a new approach to effectively remove the residual impurities and suppress the relevant dipole disorder in a low-temperature-processed (180 °C) AlOx gate dielectric layer by magnesium (Mg) doping. Mg is well known as a promising material for suppression of oxygen vacancy defects and improvement of operational stability due to a high oxygen vacancy formation energy (Evo = 9.8 eV) and a low standard reduction potential (E0 = -2.38 V). Therefore, with an adequate control of Mg concentration in metal oxide (MO) films, oxygen-related defects could be easily suppressed without additional treatments and then stable metal-oxygen-metal (M-O-M) network formation could be achieved, causing excellent operational stability. By optimal Mg doping (10%) in the InOx channel layer, Mg:InOx TFTs exhibited negligible clockwise hysteresis and a field-effect mobility of >4 cm2 V-1 s-1. Furthermore, the electric characteristics of the low-temperature-processed AlOx gate dielectric with high impurities were improved by Mg diffusion originating in Mg doping, resulting in stable threshold voltage shift in the bias stability test.

Study of E-Mode AlGaN/GaN MIS-HEMT with La-silicate Gate Insulator for Power Applications

An enhancement-mode (E-mode) AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) with La2O3/SiO2 gate insulator is investigated for high power application. The La2O3/SiO2 composite oxide formed amorphous La-silicate after post deposition annealing. Good oxide film quality and excellent La-silicate/AlGaN interface properties were achieved as evidenced by the capacitance–voltage (C–V) curves and hysteresis effect of the La-silicate on AlGaN/GaN metal–oxide–semiconductor capacitors. As a result, the E-mode AlGaN/GaN MIS-HEMT with La-silicate gate insulator shows good threshold voltage (Vth) stability and demonstrated only slightly increase in the dynamic on-resistance (Ron) after high drain bias stress test. The device also exhibits high current density of 752 mA/mm, high maximum transconductance of 210 mS/mm, low subthreshold swing of 104 mV/decade, and ION/IOFF = 107 when tested at VDS = 10 V. Furthermore, low on-resistance of 7.6 Ω mm, high breakdown voltage of 670 V, and excellent delay time of 4.2 ps were achieved, demonstrating the La-silicate MIS-HEMTs have the potential to be used for power electronic applications.

Threshold Voltage Instability of Diamond Metal–Oxide–Semiconductor Field‐Effect Transistors Based on 2D Hole Gas

Recent marked advances in diamond metal–oxide–semiconductor field‐effect transistors (MOSFETs) have raised the issue of gate reliability. Herein, the threshold voltage stability of MOSFETs based on hydrogen‐terminated diamond surface conductivity is examined. The electrical output characteristic curves are characterized by cyclic gate sweeping from reverse to forward gate bias (RF) and from forward to reverse gate bias (FR), respectively. The characteristics of drain current versus drain voltage are affected by the gate bias sweeping direction. Marked hysteresis is also observed in the transfer curves for the RF and FR gate sweeping. The different gate sweeping directions induce threshold voltage variation and hole mobility change. The facts that 1) no extra interface states are generated due to gate sweeping and 2) the trapped charge density depends on the gate oxide thickness, reveal that charge trapping occurs at the border of the gate oxide.

A 1200-V GaN/SiC cascode device with E-mode p-GaN gate HEMT and D-mode SiC junction field-effect transistor

A 1200-V/100-mΩ GaN/SiC cascode device is demonstrated with small capacitances for fast switching speed, no dynamic ON-resistance (RON) degradation, and stable high-temperature threshold voltage (VTH). To identify its safe operation in the OFF-state with a high drain bias, the middle point voltage (VM) between the GaN and SiC devices is investigated under static and dynamic modes. An adequately low VM is achieved at both static and dynamic states. A voltage distribution process found that the OFF-state VM is capacitance-dependent during the turn-off transient and turns to be resistance-dependent to match the leakage current with a steady drain bias.

(Invited) Selected Issues for SiC Mosfet Reliability

There remain a number of potential reliability issues associated with SiC power MOSFETs that interest the reliability standards community, of which this work will provide an overview of our understanding of three of those issues: (1) threshold-voltage stability; (2) body-diode robustness; and (3) short-circuit current robustness. A recent survey of commercially-available devices shows a wide range of responses in threshold-voltage stability, which is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias, necessitating the need for faster measurements and the maintenance of the stress bias before making post-stress measurements. The observation of the activation of additional traps during bias-temperature stress in older devices underlines the need for additional attention to high-temperature charging effects as well. It is the case for at least one commercial vendor, that improvement in lower BPD density and enhanced device fabrication have led to significant improvements in body-diode robustness. Earlier vintage devices had showed varying levels of degradation in both the body diode and MOSFET on-state properties following current stress of the body diode, as well as degradation in the off-state drain leakage current. Experimental results show that both commercially-available planar and trench SiC MOSFETs have suitable short-circuit (SC) withstand times, ranging from 6 to 13 μs at T = 25 °C, VGS = 20 V, and VDS = 600 V. Even when trench devices have an identical rating to planar devices, they likely will have a significantly smaller area and heat conducting volume, contributing to their lower robustness for the same SC test conditions. All the electrical results reported seem to be consistent with thermally-driven failure mechanisms. The official standard test method of a single, long pulse is found to not be as effective as a series of shorter, incremental gate pulses, which more accurately detect failure time, even in the case of latent or delayed failure. All this work will be presented within the context of standards development within JEDEC, including a number of SiC-focused reliability task groups.

1200 V SiC MOSFETs with Stable V&lt;sub&gt;TH&lt;/sub&gt; under High Temperature Gate Bias Stress

In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

Solution-based flexible indium oxide thin-film transistors with high mobility and stability by selective surface modification

Improved performances of solution-based flexible indium oxide (In2O3) thin-film transistors (TFTs) was achieved by introducing clear-cut edges of the active areas on substrate surfaces. Patterned areas for the In2O3 active regions were converted to hydrophilic by oxygen plasma treatment whereas the remaining areas between the active region patterns were converted to hydrophobic by transferring oligomer molecules from a partially cured polydimethylsiloxane (PDMS) mask. This way, In2O3 precursor could be settled only on the intended patterns for the active regions and therefore the active regions were formed with distinct edges and regular shapes. A model TFT prepared via this method exhibited significantly improved performances over a reference device prepared without the selective surface treatment in terms of threshold voltage (Vth), subthreshold swing (SS), saturation mobility (μsat), off-state current (Ioff), and bias-stress stability. Furthermore, the TFT exhibited good electrical stability under a bias stress and sustainable mechanical stability even at 10,000 cycles of bending tests at a radius of curvature of 5 mm. Such improvements were attributed to decreased trap state density at the channel/dielectric interface due to clear distinction of the active region edges and good interface properties, which also helped improving the mechanical stability under prolonged cyclic bending.

Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.

Performance improvement in 4H-SiC(0001) p-channel metal-oxide-semiconductor field-effect transistors with a gate oxide grown at ultrahigh temperature

We fabricated 4H-SiC(0001) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with gate oxide formed at 1600 °C under an oxygen partial pressure of 0.3 kPa. The fabricated pMOSFETs showed superior performance, suggesting suppression of carbon-related defects at the SiO2/SiC interface. A further performance improvement was achieved by subsequently employing forming gas annealing at 1200 °C. In particular, a peak field-effect mobility of up to 13 cm2V−1 s−1, 11% of the intrinsic hole mobility, was demonstrated. Moreover, the transistors had a stable threshold voltage up to 200 °C and high immunity against bias-temperature stress, suggesting improved reliability.

The Influence of Temperature Storage on Threshold Voltage Stability for SiC VDMOSFET

Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆VTH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.

Normally-off recessed-gate AlGaN/GaN MOS-HFETs with plasma enhanced atomic layer deposited AlOxNy gate insulator

We developed a high-quality plasma enhanced atomic layer deposited (PEALD) aluminum oxynitride (AlOxNy) process for the metal-oxide-semiconductor (MOS) gate insulator of fully-recessed-gate AlGaN/GaN-on-Si MOS-heterojunction field-effect transistors (MOS-HFETs). It was found that the cyclic nitrogen incorporation into aluminum oxide (Al2O3) during PEALD process improved the conduction band offset at GaN interface resulting in higher forward breakdown field strength, which also contributed to suppressed trapping effects under forward gate bias stress. Improved interface characteristics, which resulted from suppressed surface oxidation, led to significant improvement of threshold voltage stability. A low threshold voltage hysteresis of 180 mV at maximum gate sweep voltage of 10 V was obtained with AlOxNy gate insulator. The MOS channel mobility was also improved to 235 cm2 V−1 s−1. The fabricated fully-recessed-gate AlGaN/GaN-on-Si MOS-HFET with PEALD AlOxNy gate insulator exhibited excellent overall performances such as a threshold voltage of 3.2 V, a maximum drain current density of 481 mA mm−1, an on/off current ratio of ∼1010, an ON-resistance of 12 mΩ mm, and a breakdown voltage of 1050 V.

Enhanced Gate Reliability in GaN MIS-FETs by Converting the GaN Channel into Crystalline Gallium Oxynitride

We demonstrated the enhanced threshold voltage (VTH) stability and gate reliability of the enhancement-mode (E-mode) GaN-based MIS-FETs under reverse-bias stress (i.e., stress at off-state with high drain voltage), which is achieved by converting the conventional GaN (Eg ∼ 3.4 eV) channel into a crystalline GaOxN1–x (Eg ∼ 4.1 eV) layer. In the MIS-FETs stressed at off-state with a large drain voltage, holes will be generated in the high-electric-field region by impact ionization, and subsequently, degradation of the gate dielectric is caused by the holes passing through the dielectric film. As the valence band offset between the GaOxN1–x and GaN is ∼0.6 eV, an energy barrier for holes will be formed surrounding the gate, which can prevent holes from flowing to the gate side and therefore reduce the hole-induced gate dielectric degradation. The crystalline gallium oxynitride layer converted from GaN could also be a promising method to improve channel reliability for many GaN-based structures and processes.

Model Development for Threshold Voltage Stability Dependent on High Temperature Operations in Wide-Bandgap GaN-Based HEMT Power Devices.

Temperature-dependent threshold voltage (Vth) stability is a significant issue in the practical application of semi-conductor power devices, especially when they are undergoing a repeated high-temperature operation condition. The Vth analytical model and its stability are dependent on high-temperature operations in wide-bandgap gallium nitride (GaN)-based high electron mobility transistor (HEMT) devices that were investigated in this work. The temperature effects on the physical parameters—such as barrier height, conduction band, and polarization charge—were analysed to understand the mechanism of Vth stability. The Vth analytical model under high-temperature operation was then proposed and developed to study the measurement temperatures and repeated rounds dependent on Vth stability. The validity of the model was verified by comparing the theoretical calculation data with the experimental measurement and technology computer-aided design (TCAD) simulation results. This work provides an effective theoretical reference on the Vth stability of power devices in practical, high-temperature applications.

Enhanced gate stack stability in GaN transistors with gate dielectric of bilayer SiNx by low pressure chemical vapor deposition

We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich SiNx interlayer was deposited before a high-resistivity SiNx layer by low pressure chemical vapor deposition. The Si-rich SiNx can effectively suppress the trapping phenomenon at the interface of the dielectric/AlGaN barrier. The upper high-resistivity SiNx layer can greatly block the gate leakage current to enable a large gate swing. Compared with the MISHEMTs using a single Si-rich or high-resistivity SiNx layer, the MISHEMTs with a bilayer gate dielectric take the advantages of both, realizing a gate stack with a stable threshold voltage and low leakage current. These results thus present great potential for developing high-performance GaN MISHEMTs using the bilayer SiNx gate dielectric scheme for highly efficient power applications.

Passive–active oxidation boundary for thermal oxidation of 4H-SiC(0001) surface in O2/Ar gas mixture and its impact on SiO2/SiC interface quality

We explored the passive–active oxidation boundary for the thermal oxidation of a 4H-SiC(0001) surface. The O2 partial pressure [P(O2)] for passive–active transition was found to be around 0.03 and 0.3 kPa at 1500 and 1600 °C, respectively. We also found that the passive–active oxidation boundary for an Al-implanted surface shifted to a slightly higher P(O2). A metal–oxide–semiconductor field-effect transistor with a gate oxide formed under P(O2) of 0.3 kPa at 1600 °C demonstrated a field-effect mobility of 9.7 cm2 V−1 s−1, which was three times higher than that for a reference sample oxidized in atmospheric oxygen ambient at a moderate temperature and a high threshold voltage stability.