Characterization of Static and Dynamic Behavior of 1200 V Normally off GaN/SiC Cascode Devices

Abstract

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p -GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on -resistance ( R ON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage ( V TH), and no dynamic R ON degradation. To identify its safe operation in the off -state with a high drain bias, the off -state middle point voltage ( V M) between the E-mode device drain and D-mode device source is investigated. A relatively low off -state V M is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic V TH shift; and 2) suppress the increased dynamic off -state leakage current ( I OFF) induced by on -state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn- on and 121 V/ns during turn- off is achieved.