Abstract

An all-wide-bandgap (all-WBG) cascode device with a low-voltage (LV) enhance-mode (E-mode) p-GaN gate HEMT as the control device and a high-voltage (HV) depletion-mode (D-mode) SiC JFET as the voltage blocking device has been systematically studied. The demonstrated device with a breakdown voltage (BV) rating of 1200 V and a static ON-resistance (R ON ) of 100 m$\Omega$, features small device capacitances, avalanche breakdown capability, thermally stable threshold voltage (V TH ), no dynamic R ON degradation, and small gate charge (Q G ). To identify its safe operation in the OFF-state with a high drain bias, the OFF-state middle point voltage (V M ) between the E-mode device drain and D-mode device source is investigated. An adequately low OFF-state V M is achieved under both static and dynamic modes. Furthermore, a double-pulse test circuit is built to evaluate the transient switching performance at $25^{\circ}C$ and $150^{\circ}C$. Under 800-V/16-A testing conditions, high switching speed with low total switching losses of $214 \mu J$ and $236 \mu J$ are obtained at $25^{\circ}C$ and $150^{\circ}C$, respectively.

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