SRAM Cell Stability Research Articles

Leakage Power Attack-Resilient Design: PMOS-Reading 9T SRAM Cell

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design.

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Impact of total ionizing dose on the alpha-soft error rate in FDSOI 28 nm SRAMs

Synergy effect of total ionizing dose (TID) on alpha-soft error rate (α-SER) in FDSOI 28 nm SRAM has been experimentally characterized using a dedicated setup combining alpha-particle irradiation (241Am solid source) in vacuum chamber and 10 keV X-ray irradiation. Measurements have been performed on a 3 Mbit single-port SRAM cut powered at 1 V. Irradiations up to 125 krad(Si) have been achieved and their impact on the α-SER has been characterized from the cumulated number of bitflips as a function of the exposition time to the alpha-source. Modelling and simulation have been used to link transistor threshold voltage variations to SRAM cell stability in terms of static noise margin (SNM), critical charge (Qcrit) and finally estimated SER, in good agreement with experimental results.

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology

Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology

SRAM CELL 6T AND 8T PARAMETRIC STABILITY ANALYSIS

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

Robust Low Power Transmission Gate (TG) based 9T SRAM cell with Isolated Read and Write Operation

Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9T SRAM cell with independent read/write operation and compares its performance with 6T, 8T, and 10T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.

Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis

Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the ${K}$ design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these ${K}$ parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell.

Design of an enhanced write stability, high-performance, low power 11T SRAM cell

ABSTRACT In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which improves the stability in all operating modes of SRAM as well as the delay and power in the write mode. At worst process corner SS, the write 0 delay has been improved by 14.01%, 6.75%, 115.72% and 26.61% compared to 6 T, 8 TG, 10 TDiff and 11 T SRAM designs and write 1 delay has been improved by 9.2%, 88.639%, 13.69% and 71.42% compared to 6 T, 10 TDiff, DDS11T and 11 T designs at 0.9 V supply voltage. The impact of PVT variations has been studied on SNM, Write Margin, Read & Write delay, Leakage Power. The Monte Carlo simulation has been performed to study the effect of variability. P11T SRAM cell exhibits narrower spread in the distribution of majority design metrics. The removal of the half-select issue has been illustrated in the P11T SRAM cell using Monte Carlo simulations. Post-Layout simulation has been carried out to evaluate different design metrics at 45 nm technology node in Cadence Virtuoso.

Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells

In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.

TCAD‐based statistical modeling methodology for nanoscale FinFET variability

AbstractWe demonstrated in this article a TCAD‐based (TCAD is defined as Technology Computer Aided Design) statistical modeling methodology for FinFET devices, which included TCAD Monte Carlo simulation, SPICE model library buildup, and model verification in circuit level. As a demonstrative example, a set of 14 nm FinFET devices are investigated for TCAD variability simulation and statistical model development. The stability and variability of different SRAM cells are further evaluated to verify the applicability of proposed statistical modeling methodology. The demonstrative statistical modeling method in this article is fully compatible with industrial standard methodology of CMOS device model, which can be easily immigrated into advanced technologies.

Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits

In this work, negative bias temperature instability/positive bias temperature instability (NBTI/PBTI) reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature. We have incorporated the NBTI/PBTI $\text{V}_{\mathrm{ T}}$ model in a physics-based SiNW FET Verilog-A compact model for circuit analysis. For the first time, using integrated model, we report time zero variability and BTI reliability of the core logic gates (INVERTER, NAND, and NOR) and read/write stability of 6T SRAM cell. We demonstrate that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. The benchmarking of BTI in SiNW FET with FinFET and planar devices show SiNW have higher degradation, however it can be minimized by using optimized SiNW FET configuration. Further, we show that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the read noise margin (RNM) by 15–30%, and write noise margin (WNM) improves by 5–8% for 10-Year lifetime. We find that the combined impact of time zero variability and BTI reliability degrades the mean value of circuit delay and SRAM RNM stability, however, the degradation is found to be comparable to the reported planar and FinFET data. It is also seen that different configuration increases BTI variability (~5-25% increase) which can be minimized. Using the results, we propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate SiNW FET design configuration. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis.

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET. In this paper, we have designed and simulated 6T SRAM array operating at room temperature and at CMOS comparable voltage. Peripheral circuit like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 8 x 8 bit SRAM is 99.54 % power efficient, 92.19 % faster in write access time and 78.58 % faster in read access time compared to 16 nm CMOS based SRAM. The SRAM is designed to work at CMOS comparable voltage of 800 mV, which can be scaled up to 20 mV with better efficiency. The designed SRAM is tested and verified for variation in process, voltage and temperature. The maximum frequency of operation for the designed SET based SRAM with memory controller is 4 GHz.

Static Noise Margin of 6T and 8T SRAM Cell in 28-nm CMOS

Integrated circuits are more prone to noise at nanolevel as they are constrained in smaller area which leads to the generation of noise signal due to supply lines and other sources. It degrades the stability and performance of the circuit. SRAM is the best example of integrated circuit. SRAM is mainly used in high performance circuits and in portable devices where we require energy efficient memory. To reduce power dissipation, we reduce supply voltage which helps in reducing static power dissipation. But at the same time, stability of memory is degraded. Hence, it is essential to keep correct functioning in the presence of a noise source. This paper shows the stability of 6T and 8T SRAM cell on the basis of static noise margin computed using Cadence Virtuoso Design Environment at 28nm CMOS technology. Cells are operated at two different voltages 1.05V and 0.5V. Results are obtained for Hold margin, Read Margin and write margin at process corner variations. Result shows that improved noise margin is obtained by reducing supply voltage. At lower voltage, noise margin should be as high as possible. In 8T we get the improved noise margin than the 6T due to decoupled read port. Hence we can say that, 8T is better than the 6T.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

Improvement of SRAM stability using read and write assist techniques

The objective of this paper is to demonstrate how to improve the read stability of the SRAM cell using the read assist technique. SRAM cell stability is the primary concern for the present and future technologies due to process variations like Vt and Vdd scaling, etc. So it requires additional circuit techniques such as write and read to assist to improve the stability of SRAM memories. To accomplish the non-destructive read operation, we need to either weaken the pass transistor or strengthen the pull-up transistor during the read operation. Towards decrease of pass transistor strength, we implemented the lower word line voltage as read assist circuit. The lower word line voltage will help the selected and un-selected columns (for higher column mux options) during a read operation. But during write operation the lowered word line voltage scheme will impact the write operation. So, in order to improve the read margin we used read assist technique at the same time to ensure that write operation is successful we combined the negative bit line write assist scheme along with read assist technique. The proposed assist circuit gain the power and read margin improvement of 10%, 30% respectively. We observed the read margin analysis at process, voltage and temperature corners.

RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information

Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.

Write and Read Assist Techniques for SRAM Memories in Nanometer Technology

SRAM cell stability is the primary concern for future technologies due to process variations like threshold voltage and supply voltage scaling etc. The increased effect of process variation and increase in parasitic resistance and capacitance in Nano scale technologies, the lower supply voltages, continuous increase in the size of SRAMs requires additional techniques such as write assist and read assist to improve the write-ability, readability and stability of SRAM memories. In this paper various write and read assist techniques are analyzed with their pros and cons and each technique is explained with their implementation and their impact on write-ability, readability and stability of the SRAM memory. The SRAM bit cell write-ability is very critical at lower voltages. The impact of the write assist technique analyzed across the process, voltage and temperature range. Along with improving the write-ability of the SRAM cell the write assist techniques will impact the performance, power and area of the chip. At lower voltages the noise margin is very crucial for the SRAM cell stability. Read assist techniques help in improving the cell stability and these techniques analyzed across the process, voltage and temperature range. These read assist techniques not only helps the readability and stability of SRAM bit cells but they also will impact the performance, power and area of the chip.

An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization.