Write and Read Assist Techniques for SRAM Memories in Nanometer Technology

Abstract

SRAM cell stability is the primary concern for future technologies due to process variations like threshold voltage and supply voltage scaling etc. The increased effect of process variation and increase in parasitic resistance and capacitance in Nano scale technologies, the lower supply voltages, continuous increase in the size of SRAMs requires additional techniques such as write assist and read assist to improve the write-ability, readability and stability of SRAM memories. In this paper various write and read assist techniques are analyzed with their pros and cons and each technique is explained with their implementation and their impact on write-ability, readability and stability of the SRAM memory. The SRAM bit cell write-ability is very critical at lower voltages. The impact of the write assist technique analyzed across the process, voltage and temperature range. Along with improving the write-ability of the SRAM cell the write assist techniques will impact the performance, power and area of the chip. At lower voltages the noise margin is very crucial for the SRAM cell stability. Read assist techniques help in improving the cell stability and these techniques analyzed across the process, voltage and temperature range. These read assist techniques not only helps the readability and stability of SRAM bit cells but they also will impact the performance, power and area of the chip.