Abstract
As supply voltage scales down, the leakage energy starts to dominate the total power. This paper presents a single ended 9T SRAM bit cell which operates at subthreshold voltages. With design techniques like feedback cutting schemes and ground cut-off both read ‘1’ and write ‘0’ power reduced by nearly 50% in contrast to the reference 8T SRAM cell. The write ‘0’ timing is 30% lesser than the 8T cell at low supply voltages with stable read and write operations for voltages as low as 200mV. The functionality of the cell has been validated at various process corners.
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