A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

Abstract

The need for power-efficient memories that are capable of operating at low supply voltages has led to the development of several alternative bit cell topologies. The majority of the proposed designs are based on the 6T bit cell with the addition of devices and/or peripheral techniques aimed at reducing leakage and enabling read and write functionality at lower operating voltages. In this brief, we propose a reduced transistor count bit cell that is fully functional in the sub-threshold (ST) region of operation. This asymmetric 5T bit cell is operated through a single-ended read and differential write scheme, with an option for operation as a two-port cell with single-ended write. The bit cell's operating scheme provides a non intrusive read operation and improved write margins for robust functionality. In addition, the circuit's asymmetric characteristic provides a low-leakage state with an additional 5X static power improvement over the reduction inherently achieved through voltage lowering. The proposed bit cell was designed and simulated in a 40-nm commercial CMOS process and is shown to be fully operational at ST voltages as low as 400 mV under global and local process variations. At this supply voltage, a 21X static power reduction is achieved, as compared to the industry-standard 6T bit cell, operated at its minimum supply voltage.