Improvement of SRAM stability using read and write assist techniques

Abstract

The objective of this paper is to demonstrate how to improve the read stability of the SRAM cell using the read assist technique. SRAM cell stability is the primary concern for the present and future technologies due to process variations like Vt and Vdd scaling, etc. So it requires additional circuit techniques such as write and read to assist to improve the stability of SRAM memories. To accomplish the non-destructive read operation, we need to either weaken the pass transistor or strengthen the pull-up transistor during the read operation. Towards decrease of pass transistor strength, we implemented the lower word line voltage as read assist circuit. The lower word line voltage will help the selected and un-selected columns (for higher column mux options) during a read operation. But during write operation the lowered word line voltage scheme will impact the write operation. So, in order to improve the read margin we used read assist technique at the same time to ensure that write operation is successful we combined the negative bit line write assist scheme along with read assist technique. The proposed assist circuit gain the power and read margin improvement of 10%, 30% respectively. We observed the read margin analysis at process, voltage and temperature corners.