An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Abstract

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.