Run Time $V_{th}$ Extraction Based On-Chip NBTI Mitigation Sensor for 6T SRAM Cell

Abstract

The aggressive scaling of the CMOS technology has made negative bias temperature instability (NBTI) a key concern in device reliability. The NBTI effect increases the threshold voltage $(V_{th})$ and decreases the drain current of PMOS with time. This paper present a Run time $V_{th}$ extraction based NBTI sensor to mitigate the aging effect. Here a close loop system is proposed to compensate the degradation in performance parameter of 6T SRAM cell. The proposed model consists of four modules such as run-time threshold voltage extractor module(aging sensor), voltage generator module, decision making module and transistor width auto-resizer module. All the modules are designed and investigated using PTM 45nm CMOS technology. Circuit level simulation on SRAM cell are performed in pre and post stress condition for 6 years of NBTI effect. The simulation result shows that the threshold voltage is increased by 14.77% which in turn degrades the drain current by 12.8% in 6 year of NBTI effect. Simulation result also shows that the Read SNM and Hold SNM are decreased by 18.59% and 2.97% and Write SNM is increased by 1.6% in 6 year of NBTI stress. It is observed that the proposed sensor increases the drain current to its actual value by just oversizing the width of NBTI affected PMOS transistor by 35.8% and mitigate the effect of NBTI on SRAM cell.