NBTI and Its Effect on SRAM

Abstract

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V TH transistors age faster than the high V TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V TH with technology scaling. Also NBTI effect is more significant at higher temperature.