NMOS Only Schmitt Trigger Based SRAM Cell

Abstract

The scaling of transistors to nanoscale and even lower requires them to be operated in sub threshold region of operation. Negative Bias Temperature Instability (NBTI) is a quantum effect observed in p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that takes place due to operation at sub threshold voltages. NBTI reduces the lifetime of the circuit by degrading the performance. The effect of NBTI in standard 6T Static Random Access Memory (SRAM) cell can be reduced by replacing the inverter with NMOS only Schmitt trigger inverter. The simulation of proposed NMOS only Schmitt trigger based SRAM cell is carried out at 0.6 V in 45 nm gpdk technology in Cadence Virtuoso. The Static Noise Margin (SNM) of the proposed design with respect to standard 6T SRAM cell has doubled in write mode and has increased by 66.66 percent in read mode as seen in the simulation results obtained.