SRAM Bitcell Research Articles

Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM).

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset

This research paper introduces a memory architecture that handles standard memory storage operations and enables in-memory computations, surpassing the capabilities of conventional SRAM bit-cells. The proposed architecture in this work effectively eliminates read-disturb issues and facilitates bit-wise operations like NAND, NOR, and XNOR, all without requiring intricate analog peripheral circuits. The suggested bit-cell architecture offers enhanced throughput compared to existing In-Memory Computing (IMC) bit-cell architectures, making it a more suitable design for IMC applications. Parallelism offers enhanced throughput due to the unique bit-cell architecture, which allows all the bit-wise operations to be achieved simultaneously in a single cycle. The validity of the suggested architecture has been confirmed through Monte-Carlo variation analysis, utilizing UMC 28 nm PDK transistor models to ensure its robustness. Furthermore, architecture is benchmarked using the CIFAR-10 dataset, which entails assessing its performance across various machine learning models via the NeuroSim Simulator. The proposed architecture offers a substantial increase of up to 40 % in throughput (TOPS/W) compared to the existing architectures. Utilizing accurate Monte-Carlo simulations with 1000 samples, the stability of the proposed 10T bit-cell is validated at worst-case PVT corners, up to 6σ variations.

Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

As the technology has rapidly evolved and also high-speed task implementation has come into picture the chance for an error to occur has also increased though there are many precision algorithms to increase the precision of the system significantly this paper proposes one such error reducing application for aerospace applications. Using a Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications (QUCCE12T) is more susceptible to data loss as the QUCCE12T SRAM has high sensitivity and the sensitive nodes are at higher risk. To reduce this, we propose to use Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM (SREWH12T). Basically, the initial thought is to reduce the soft error created by voltage drops by passing the data through the inverters. The Single Event Upset (SEU) that arise in the usage of QUCCE12T SRAM can be recovered using a SREWH12T SRAM instead. The sensitive components of SREWH12T have the capability to recover their data even in cases where the values have been altered by radiation impact. The SREWH12T SRAM cell to mitigate upsets, compares it with other cells, and demonstrates its superior performance in terms of soft-error tolerance, recovery from upsets and having low power consumption. Furthermore, the added advantage of SREWH12T cell is that it can recover from Single Event Multiple Nodes Upset (SEMNU). Average power consumed by SREWH12T is 2.988363e-007 watts. Along with this the SREWH12T SRAM can provide high write stability due to its recovery rate. All these added advantages and recovery of data all comes at high utility range and with slightly high read energy consumption, which is very minimal, the system also exhibits slightly high read delay.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

A High-Precision Voltage-Quantization-Based Current-Mode Computing-in-Memory SRAM.

Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM's calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply.

Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

A promising new alternative to efficiently solve the Von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128 × 128 bitcell array based on 28 nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive defects (open and short) injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-short and resistive-open defects.

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V DD Assist and Bitline Leakage Compensation

Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based CSRAM designs. Existing solutions aim to mitigate the disturbance issue via weakening the access transistor strength, clamping the sensed bitline voltage swing, or substituting with read-decoupled SRAM bitcell designs. However, these techniques all come with significant design overheads of performance degradation in computational read and write accesses and increased layout area. This article presents multiple circuit-level techniques for the design and optimization of a reliable and high-speed 6T-based CSRAM. First, we propose a novel dual-split- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{DD}}$</tex-math> </inline-formula> (DSV)-assisted scheme for mitigating the compute access disturbance in 6T SRAM and simultaneously improving the computational read access performance. Second, we propose a leakage-compensated asymmetrical differential sense amplifier (LCAD-SA) to further improve the compute access performance. Third, we propose a DSV-assisted columnwise write scheme for accelerating the write performance. The proposed 6T CSRAM was implemented in the 28-nm CMOS, achieving a 1.18-GHz peak operating frequency, which is a 2.36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> throughput improvement compared with that of the state-of-the-art CSRAM designs.

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network

In this paper, we present a 10T SRAM compute-in memory (CiM) macro to process the multiplication-accumulation (MAC) operations between ternary-inputs and binary-weights. In the proposed 10T SRAM bitcell, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">charge-domain</i> analog computations are employed to improve the noise tolerance of bit-line (BL) signals where the MAC results are represented in CiM. Parallel processing of 3 different analog levels for ternary input activations is also performed in the proposed single 10T bitcell. To reduce the analog-to-digital converter (ADC) bit-resolutions without sacrificing deep neural network (DNN) accuracies, a confined-slope non-uniform integration (CS-NUI) ADC is proposed, which can provide layer-wise adaptive quantization for multiple different layers with different MAC distributions. In addition, by sharing the ADC reference voltage generator in every single column of SRAM array, the ADC area is effectively reduced with improved energy efficiencies of CiM. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256\times64.10$</tex-math> </inline-formula> T SRAM CiM macro with the proposed charge-sharing scheme and CS-NUI ADCs has been implemented using 28nm CMOS process. The silicon measurement results show that the proposed CiM shows the accuracies of 98.66% and 88.48% with MNIST dataset on MLP, and CIFAR-10 dataset on VGGNet-7, respectively, with the energy efficiency of 2941-TOPS/W and the area efficiency of 59.584-TOPS/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> .

Single-sided gate-wrap-around CNTFET SRAM cell for utilization in reliable IoT-based platforms

This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively.Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture.

Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off.

Transposable 9T-SRAM Computation-In-Memory for on-Chip Learning With Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices

This work proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bitcell conducts local two-way computing without shared processing units, achieving higher processing throughput from every bit-cell operating in one CIM cycle. This work also proposes a probabilitybased single-slope (SS) and successive approximation (SAR) hybrid analog-to-digital converter (ADC) for energy efficiency improvement by utilizing the probability density function of multiply-and-accumulation (MAC). The proposed ADC also supports the ReLU-based zero skip function without additional circuitry. The prototype was fabricated in 180nm CMOS technology and achieved an energy efficiency of 6.61 (1.65) TOPS/W for inference (training).

A sub-threshold 10T FinFET SRAM cell design for low-power applications

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM.

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of <inline-formula> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2^N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm², respectively.

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

This paper proposes a novel design of ultra-low power radiation-hardened single-ended SRAM bit-cell using the gate-all-around CNT-MOSFET based-gate diffusion input method (GAA CNT-GDI) for application in radiation-prone terrestrial (low-orbit) environments, where resources of circuit’s power supply are limited. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, in order to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate expand write/hold/read static noise margins about 12.5%, 3.8%, and 8.2%, other figure of merits (FoMs), such as performance, yield, variability (μ/σ) and critical charge about 6.4 %, 5.8 % and almost 1.19 times respectively compared to studied cell design in counterpart technologies. Moreover, the suggested bit-cell has more robustness against radiation-induced soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in terms of other comprehensive FoMs as compared to state-of-the-art bit-cells in the 16 nm technology. The proposed bit-cell in a real application is used to store data from two-layer quick-response (2LQR) code-based in safety-critical environments. The results show the better performance of bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs. Finally, the simulation results have validated that the suggested memory architecture can be a suitable candidate for application in devices such as terrestrial satellites that require both high reliability and cost-effectiveness.

DATIC: A Data-Aware Time-Domain Computing-in-Memory-Based CNN Processor With Dynamic Channel Skipping and Mapping

Due to the low-power priority of analog delay-based computation, time-domain computing-in-memory (TD-CIM) presents a splendid potential for energy-constrained edge and IoT scenarios deploying convolutional neural networks (CNNs). However, the latency in delay-based computation is proportional to the numbers and values of multiplications-and-accumulations (MACs), bottlenecking the throughput of previous data-agnostic TD-CIM-based processors which compute complete convolutions in a fixed MAC mapping manner. Firstly, some output activations in each layer of CNNs contribute less to the final classification results, which are insignificant and can be substituted by sums of partial MACs, with a marginal accuracy degradation. Thus, complete convolution computations lead to redundant MACs. Secondly, activations and weights vary with input images and models. Fixed MAC mapping leads to unbalanced MAC values on delay chains, causing long idle time and latency. To address that, we design a data-aware TD-CIM-based CNN processor, DATIC, with three techniques to reduce latency: 1) A channel-skipping TD-CIM macro to remove redundant MACs for insignificant output activations, by storing activations stationary in SRAM bitcells and shifting weights to perform only imperative MACs; 2) A convolution order programming unit to reduce overhead of skipping redundant MACs for insignificant output activations with random positions on feature maps; 3) An activation-weight-adaptive channel-mapping scheduler to balance latency of delay chains by dynamically altering convolution mapping manner. Implemented under TSMC 28-nm technology, DATIC achieves 622.9GOPS throughput and 32.7TOPS/W energy efficiency for ResNet-18 with 2-b weights and 8-b activations.

SRAM design leveraging material properties of exploratory transistors

While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.

A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.

Newly energy-efficient SRAM bit-cell using GAA CNT-GDI method with asymmetrical write and built-in read-assist schemes for QR code-based multimedia applications

The novel design of asymmetric single-ended ten-transistor SRAM bit-cell (SE 10T-SRAM) using gate-all-around (GAA) carbon nanotube (CNT) FETs-based GAA CNT-GDI method along with dual-chirality technique for CNTs, the asymmetric write-assist and built-in read-assist schemes in the presence of more saving area and less energy consumption is suggested for portable/mobile multimedia applications. Based on the analytical-compact model, an equation for calculating write-static margin (WSNM) is presented by expressing the degree of dependence of the metric on the power supply voltage variation for the suggested bit-cell structure. The results of extensive simulations to evaluate the proposed bit-cell in single and multi-array structures indicate better static/dynamic noise margins, less sensitivity to process, voltage and temperature (PVT) variations, improvement of basic parameters in the presence of contact length changes, more noise-immunity with scalability at cell supply voltage, and better results in other comprehensive figure of merits (FoMs) parameter compared to nanotechnology-based counterpart circuits with the same number of transistors in the 16 nm technology node. Also, evaluating the proposed structure in the presence of changes in the contact length parameter of other transistors as a contact length sizing-level solution, indicating the achievement of an improved structure in the basic parameters such as static noise margin, power consumption, and energy-delay product (EDP) parameter compared to the default structure with a minimum-sizing contact length. Finally, in order to use the proposed bit-cell in a real application, the suggested structure for storing images based on quick response (QR) code is examined with a link between MATLAB and synopsys H-SPICE simulator tools based on suggested algorithm. The results demonstrate that the suggested bit-cell is with more appropriate and significant results in terms of comprehensive FoMs, in which the evaluations concerning the appropriate accuracy in pixel-by-pixel storage of images based on the peak signal-to-noise ratio (PSNR) and the mean structural similarity index measure (MSSIM) metrics, compared to other well-known counterpart schemes confirms the superiority of the proposed design. Hence, the proposed design can be used for various areas regarding multimedia device applications.

Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM

A refresh free and scalable ultimate DRAM (uDRAM) with 1T1C bitcell is introduced in this paper. The memory uses the Negative Differential Resistance (NDR) property of Tunnel Field Effect Transistors (TFET) and storage capacitor leakage to retain data statically. The static data retention eliminates the need for refresh. The uDRAM allows more than 5x scaling of a storage capacitor in comparison to Dual-Data-Rate (DDR) and embedded DRAMs. This concept is further extended to design a 2T1C ultimate SRAM (uSRAM) and 3T1C ultimate CAM (uCAM). Area of 0.0275 μm2, 0.07 μm2 and 0.104 μm2 are achieved for DRAM, SRAM and CAM bitcells, respectively, when implemented in TFET-compatible 28 nm FDSOI-CMOS process. The uDRAM achieves an estimated throughput gain up-to 9.94% in comparison with a CMOS DRAM, owing to refresh removal in the DDR configuration. The 2T1C SRAM with read and write cycle times of sub-2ns and sub-4ns are demonstrated. The results show ultra-low leakage of less than 1 fA/bit for the proposed designs.

A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks

A novel 4T2C ternary embedded DRAM (eDRAM) cell is proposed for computing a vector-matrix multiplication in the memory array. The proposed eDRAM-based compute-in-memory (CIM) architecture addresses a well-known Von Neumann bottle-neck in the traditional computer architecture and improves both latency and energy in processing neural networks. The proposed ternary eDRAM cell takes a smaller area than prior SRAM-based bitcells using 6-12 transistors. Nevertheless, the compact eDRAM cell stores a ternary state (-1, 0, or +1), while the SRAM bitcells can only store a binary state. We also present a method to mitigate the compute accuracy degradation issue due to device mismatches and variations. Besides, we extend the eDRAM cell retention time to 200μs by adding a custom metal capacitor at the storage node. With the improved retention time, the overall energy consumption of eDRAM macro, including a regular refresh operation, is lower than most of prior SRAM-based CIM macros. A 128×128 ternary eDRAM macro computes a vector-matrix multiplication between a vector with 64 binary inputs and a matrix with 64 × 128 ternary weights. Hence, 128 outputs are generated in parallel. Note that both weight and input bit-precisions are programmable for supporting a wide range of edge computing applications with different performance requirements. The bit-precisions are readily tunable by assigning a variable number of eDRAM cells per weight or adding multiple pulses to input. An embedded column ADC based on replica cells sweeps the reference level for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sup> -1 cycles and converts the analog accumulated bitline voltage to a 1-5bit digital output. A critical bitline accumulate operation is simulated (Monte-Carlo, 3K runs). It shows the standard deviation of 2.84% that could degrade the classification accuracy of the MNIST dataset by 0.6% and the CIFAR-10 dataset by 1.3% versus a baseline with no variation. The simulated energy is 1.81fJ/operation, and the energy efficiency is 552.5-17.8TOPS/W (for 1-5bit ADC) at 200MHz using 65nm technology.