SRAM Bitcell Research Articles

Implementation of 12T and 14T SRAM Bitcell Using FinFET with Optimized Parameters

In this paper, we have implemented 12T and 14T SRAM bitcell using FinFET with optimized parameters. Optimized parameters are related in terms average power consumption, delay, power delay product (PDP), and energy delay product (EDP). Simulation results of all parameters of 12T and 14T SRAM bitcell are reported with 22 nm FinFET technology. All parameters of 12T and 14T SRAM using FinFET are compared to conventional 12T and 14T SRAM and found that the results have improved in average power consumption, PDP, EDP, and propagation delay. Parameters for 12T SRAM using FinFET includes average power consumption, propagation delay, PDP and EDP, which are improved by 99%, 79.2%, 99.7% and 99.7%, respectively. Similarly, designing 14T SRAM using FinFET, gets improvements of 99% in Average Power consumption, 76.5% in propagation Delay, 99.4% in PDP, and 99.5% in EDP.

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vˆddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vˆddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on Vddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our Vddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.

Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation

In this article, a novel asymptotic probability approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient hierarchical subset simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimate the overall failure rate of correlated rare failure events involving more than 20 000 independent random variables.

Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers

N×N filter operations are frequently used in various image processing algorithms in display driver circuits. The implementation of the N×N filter requires a storage element to temporarily retain N or N-1 lines of display data. The traditional approach for this temporary storage element for N×N image filter is either by using N blocks of memory to store N lines of display data with single-port six-transistor (6T) SRAM bit-cells or by using N-1 blocks of memory to store N-1 lines of display data with dual-port eight-transistor (8T) SRAM bit-cells. In this paper, a pseudo multi-port SRAM circuit is proposed for N×N filter in image processing in a display driver integrated circuit (IC). By using pre-read mechanism and word-line/column selection signal forwarding technique, the proposed approach only stores N-1 lines of display data and can use the small single-port 6T SRAM bit-cells. For a 3×3 filter application, the proposed approach reduces the overall layout area by 50.3% and 30.2% compared to the traditional dual-port 8T and single-port 6T memory implementations, respectively, in an industrial 0.18- μm CMOS technology. Furthermore, the power used to perform a 3×3 filter operation is reduced by 47% and 30.8% with the proposed approach as compared to the traditional dual-port 8T and signal-port 6T memory circuits, respectively, with slight degradation of the access speed.

NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (Iw), respectively. Then, under process-induced random variation, sensitivities of SNM and Iw are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.

Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits

This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event–multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.

A 23.6-Mb/mm&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$^{2}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications

A 23.6-Mb/mm $^{2}$ and a 20.4-Mb/mm $^{2}$ SRAM arrays are manufactured in a 10-nm FinFET CMOS technology, utilizing high-density $0.0312~\mu \text{m}^{2}$ and low-voltage $0.0367~\mu \text{m}^{2}~6\text{T}$ SRAM bitcells. A pulsed-pMOS transient voltage collapse (PP-TVC) write assist circuit is implemented to minimize write energy overhead of the TVC write assist technique, delivering 43% write energy reduction compared to the conventional strong-bias nMOS TVC (SBN-TVC). PP-TVC also achieves up to 50-mV write $V_{\text {MIN}}$ reduction at 90th percentile, enabling 0.6-V $V_{\text {MIN}}$ for the low-voltage 6T SRAM cell (LVC). A stepped-wordline (S-WL) technique is implemented to deliver >100-mV reduction in the high-density 6T SRAM cell (HDC) write $V_{\text {MIN}}$ relative to static WL underdrive (WLUD), while achieving similar read $V_{\text {MIN}}$ , pulling the HDC $V_{\text {MIN}}$ within 35 mV of the LVC $V_{\text {MIN}}$ .

Transient Response of 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${\mu}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness

In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI (FD-SOI and PD-SOI) devices is analyzed for their transient response to heavy-ion irradiation. We have analyzed radiation performance of FD-/PD-SOI MOSFETs and 6-T SRAM bit-cells, conforming to 0.18- $\mu \text{m}$ technology node, using calibrated 2-D TCAD simulations. We, for the first time, report here that while SRAMs designed with FD-SOI devices have superior hardness to heavy-ion radiation, they are also more sensitive to SOI film thickness than the SRAMs designed with PD-SOI devices. The slopes of the critical linear energy transfer (LETC) to SOI film thickness curves are +1000 and −950 000 $\text {MeV}\cdot \text {cm/mg}$ for PD-SOI and FD-SOI devices at 1.8V supply voltage ( ${V} _{\text {DD}}$ ), respectively. The negative slope for FD-SOI device indicates better radiation performance for thinner silicon films, while a positive slope in PD-SOI device indicates better radiation performance with thicker silicon films. We further investigated the effect of ambient temperature and supply voltage ( ${V} _{\text {DD}}$ ) on SOI thickness scaled FD-/PD-SOI devices. We show that increasing ${V} _{\text {DD}}$ results in increased generated charge due to the heavy-ion at transistor level, whereas LETC of the SRAM bit-cell improves with increasing ${V} _{\text {DD}}$ . We further highlight that the heavy-ion radiation response as a function of ambient temperature depends not only on the thickness of the SOI film but also on the LET of the impinging heavy-ion.

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage ( $V_{\text {min}}$ ) can be reproduced by our test circuit. Bit density of 3.16 Mb/mm2 was achieved.

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology

PurposeThis paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approachA new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.FindingsThe proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/valueThe proposed bit-cell is novel compared with existing bit-cells.

An In-Memory VLSI Architecture for Convolutional Neural Networks

This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural and circuit techniques are proposed to address the dominant energy and delay costs associated with data movement in CNNs. The proposed architecture employs a deep in-memory architecture, to embed energy-efficient low swing mixed-signal computations in the periphery of the SRAM bitcell array. An efficient data access pattern and a mixed-signal multiplier are proposed to exploit data reuse opportunities in convolution. Silicon-validated energy, delay, and behavioral models of the proposed architecture are developed and employed to perform large-scale system simulations. System-level simulations using these models show 97% detection accuracy on the MNIST data set, along with 4.9× and 2.4× improvements in energy efficiency and throughput, respectively, leading to 11.9× reduction in energy-delay product as compared with a conventional (SRAM + digital processor) architecture.

(Invited) FDSOI: The Technology Alternative to the Mainstream

At the end of the traditional scaling of CMOS technologies, the industry started to explore paths to push for more performance in chips. This was and has always been driven by the performance-hungry high-end CPU and GPU manufacturers. The main approach was to increase the gate area per chip area by using 3D transistors instead of planar ones, i.e. FinFET. These Fins are very thin, so that in addition to the “double” gate area, the whole conducting channel becomes fully depleted. This reduces the short channel effects dramatically and thus enables a significant shrink of the channel length. However, the manufacturing of FinFET CMOS turned out to be very complex and thus costly. It took the industry more than 10 years to introduce it, first time at the 22nm node in 2011 [1]. Due to this non-planar device architecture, the chip design became much more complex so that only few design houses could afford it. In the last few years, a new trend emerged in semiconductor industries: Connecting everything with everything, also called the Internet of Things (IoT). For this space of applications, computing power does not matter as much as low leakage and/or low dynamic power at low cost. With 22FDX, GLOBALFOUNDRIES offers a technology with less complexity than FinFET, same gate length scaling due to fully-depleted channels, and additional features like back-gate biasing which perfectly suits the IoT market needs [2]. This technology offers nFET (pFET) drive currents of 910µA/µm (856µA/µm) at 0.8V and 100nA/µm leakage. It can be extended down to pA/µm transistor and pA/bitcell leakages for ultra-low leakage applications and below 0.4V Vdd operation for ultra-low dynamic power applications. At the same time, it offers RF/analog characteristics superior to FinFET with fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively, which serves a huge range of RF and millimeter wave applications. 22FDX also offers a competitive SRAM bitcell with competitive 1.46mV-μm FinFET-like transistor mismatch coefficient (AVt). Extremely low minimum operating voltages (Vmin) are reported for both the high-density (HD) 0.110μm2 and high-current (HC) 0.124μm2 bitcells without any assist, showing 95% limited yield (LY) Vmin values of 0.6V and 0.5V for 64Mb HD and 128Mb HC arrays, respectively [3]. The co-integration of SOI and bulk devices on the same wafer expands the device suite to very efficient diodes, bipolar devices, capacitors, and LDMOS. Main features are FDSOI substrate for nFET, SiGe channel for pFET and dual in-situ doped raised source/drain epitaxy. Despite the utilization of the majority of process steps from the 28nm technologies, a logic/SRAM die scaling of 0.72x/0.83x relative to the 28nm technology node is achieved. All of the above combined enables cost-efficient manufacturing. Back-gate biasing is a unique feature in FDSOI technologies which allows altering the I/V curves of individual devices up to whole blocks of circuitry to boost performance or minimize leakage wherever needed. This feature gives an additional degree of freedom to circuit and chip designers to optimize their products. Some examples will be shown. Furthermore, GLOBALFOUNDRIES is in development of 12FDX, the next FDSOI technology node, which offers further area scaling at enhanced performance and extended features.

A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability

A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability

A novel highly reliable and low-power radiation hardened SRAM bit-cell design

In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard digital CMOS technology, the simulation results show that the SRAM cell can provide full immunity for single node upset and multiple-node upset. And its critical charge is 25 times compared with Quatro10T. Besides, by comparing several electrical parameters, the proposed SRAM cell has the highly reliable and low-power capability for severe radiation environment application.

Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor

Reducing the operating voltage of digital systems improves energy efficiency, and the minimum operating voltage of a system ( $V_{\min }$ ) is commonly limited by SRAM bitcells. Common techniques to lower SRAM $V_{\min }$ focus on using circuit-level periphery-assist techniques to prevent bitcell failures at low voltage. Alternatively, this paper proposes architecture-level techniques to allow caches to tolerate significant numbers of failing bitcells at low voltage while maintaining correct operation. The presented processor lowers SRAM-based cache $V_{\min }$ using three architectural techniques–bit bypass, dynamic column redundancy , and line disable–that use low-overhead reprogrammable redundancy (RR) to increase the maximum tolerable bitcell failure rate and decrease the minimum operating voltage in processor caches. In a fabricated 28-nm RISC-V-based processor chip, these RR techniques add 2% area overhead to the cache and reduce the $V_{\min }$ of the 1-MB L2 cache by 25%, resulting in a 49% power reduction.

A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing

An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bitline (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed input–output block. Also, a configurable SRAM bitcell array is proposed to allocate the converted digital data without unfilled bitcells. The multirow access decoder selects multiple bitcells in a single column and configures the bitcell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using the 65-nm CMOS technology. It achieves 17.5-fJ/bit energy-efficiency and 21-Gbit/s throughput for the analog readout, which are 64% and 1.3 times better than those of the conventional SRAM followed by a digital-to-analog converter (DAC). Also, the area is reduced by 91% compared with the conventional SRAM with analog-to-digital converter (ADC) and DAC.