Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor

Abstract

Reducing the operating voltage of digital systems improves energy efficiency, and the minimum operating voltage of a system ( $V_{\min }$ ) is commonly limited by SRAM bitcells. Common techniques to lower SRAM $V_{\min }$ focus on using circuit-level periphery-assist techniques to prevent bitcell failures at low voltage. Alternatively, this paper proposes architecture-level techniques to allow caches to tolerate significant numbers of failing bitcells at low voltage while maintaining correct operation. The presented processor lowers SRAM-based cache $V_{\min }$ using three architectural techniques–bit bypass, dynamic column redundancy , and line disable–that use low-overhead reprogrammable redundancy (RR) to increase the maximum tolerable bitcell failure rate and decrease the minimum operating voltage in processor caches. In a fabricated 28-nm RISC-V-based processor chip, these RR techniques add 2% area overhead to the cache and reduce the $V_{\min }$ of the 1-MB L2 cache by 25%, resulting in a 49% power reduction.