Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

Abstract

As the technology has rapidly evolved and also high-speed task implementation has come into picture the chance for an error to occur has also increased though there are many precision algorithms to increase the precision of the system significantly this paper proposes one such error reducing application for aerospace applications. Using a Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications (QUCCE12T) is more susceptible to data loss as the QUCCE12T SRAM has high sensitivity and the sensitive nodes are at higher risk. To reduce this, we propose to use Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM (SREWH12T). Basically, the initial thought is to reduce the soft error created by voltage drops by passing the data through the inverters. The Single Event Upset (SEU) that arise in the usage of QUCCE12T SRAM can be recovered using a SREWH12T SRAM instead. The sensitive components of SREWH12T have the capability to recover their data even in cases where the values have been altered by radiation impact. The SREWH12T SRAM cell to mitigate upsets, compares it with other cells, and demonstrates its superior performance in terms of soft-error tolerance, recovery from upsets and having low power consumption. Furthermore, the added advantage of SREWH12T cell is that it can recover from Single Event Multiple Nodes Upset (SEMNU). Average power consumed by SREWH12T is 2.988363e-007 watts. Along with this the SREWH12T SRAM can provide high write stability due to its recovery rate. All these added advantages and recovery of data all comes at high utility range and with slightly high read energy consumption, which is very minimal, the system also exhibits slightly high read delay.