Radiation Hardening Techniques for SOT-MRAM Peripheral Circuitry

Abstract

Magnetic RAM (MRAM) is experimentally proved intrinsically immune to radiation effects including heavy-ion irradiation and total ion does [1–3] as the data is represented by the spin instead of charges. It is considered as a promising candidate for aerospace and avionic electronics. However, its CMOS peripheral read/write circuits are much more vulnerable to radiation-induced single event upset (SEU) and multi-bit upset (MBU), also called soft errors [4]. Therefore radiation hardening techniques are required to correct soft errors induced by irradiation. Currently, existing radiation hardening techniques are focused on sensing amplifiers of spin transfer torque (STT)-MRAM rather than write circuits since the write pulse is longer than the radiation-induced current pulse. However, for spin orbit torque (SOT)-MRAM, the magnetization switching time $( < 1$ns) is comparable to the width of radiation-induced pulse. Therefore write circuits for SOT-MRAM is seriously required to harden since it may be disturbed by irradiation to switch the storage state of magnetic torque junction (MTJ), which called non-volatile SEU (NVSEU) [5]. Although radiation hardening techniques of sensing amplifiers have been proposed, such as C-element and XOR logic gate [6], they cannot correct MBU induced by charge sharing especially with the decreasing process dimension. In this work, we first proposed a novel hardening peripheral CMOS read/write circuitry for SOT-MRAM shown in Fig. 1. By using a physics-based SOT-MTJ compact model and a 65nm CMOS design kit, hybrid simulations are performed to validate the radiation tolerance of the novel peripheral read/write circuitry. For write circuits, sensitive nodes are A and B shown in Fig. 1(a). Unprotected write circuits may be disturbed by NVSEU to induce incorrect magnetization switching. For hardening write circuits, wherever radiation-induced particles strike, the struck node can be recovered within hundreds of picoseconds through added redundant nodes and feedback connections. Meanwhile the incorrect magnetization state is corrected, as verified by the simulation results of Fig. 2(a). For hardening read circuits shown in Fig. 1(b) [7], sensitive nodes may be Q, Qb, S0 and S1 depending on the stored data. For example, during the clock rising edge of reading “0”, sensitive nodes are node Q, S0 and S1. Meanwhile Qb is a stable high voltage node since it is connected to PMOS transistors (when PMOS is struck, a positive transient pulse is generated [8]). Every sensitive node is immune to SEU as the following reasons: i) When node Q is turned “1” by a struck particle, S0 and S1 as cross-coupled connections retain initial states. Q is discharged through PM16 to recover. ii) When node S0 is turned “0” by a struck particle, S1 stays floating state with “0” and Qb stays throughout high voltage as the driving ability of PM12 is stronger than PM15. iii) Similarly, S1 is corrected through the similar path to S0 since the hardening read circuits are symmetrical. In addition, if nodes S0 and S1 are simultaneously struck to induce MBU, the proposed hardening read circuits also can be recovered, as shown in Fig. 2(b). Although the proposed read circuits are vulnerable to MBU for the rest multi-sensitive nodes (i.e. S0-Q and S1-Q), the solution is that using physically apart approach [9] to expand the space between sensitive nodes (the layout is omitted). More importantly, the proposed hardening read circuits effectively reduce the hardware area compared to those of the previous works [5–6]. The circuitry reliability is also validated by a Monte-Carlo statistical analysis tool taking into account process variations. This spintronic/CMOS circuitry can be reliably integrated into aerospace and avionics electronics in hostile environments.