Voltage-Gate Assisted Spin-Orbit Torque MRAM for High-Density and Low Power Embedded Applications INVITED

Abstract

Magnetic random access memory (MRAM) with its inherent non-volatility is believed to address the large stand-by energy issues in the present memory hierarchy [1]. In recent years, the spin-transfer torque (STT)-MRAM has gradually matured and started to appear in the market. Typically, STT writing of perpendicular magnetic tunnel junction (pMTJ) is limited to a few nanoseconds. This is because STT is collinear and competing with the intrinsic damping of the free-layer (FL), resulting in a long incubation delay [2] and large energy consumption. To mitigate STT limitations, spin-orbit torque (SOT) and voltage control of magnetic anisotropy (VCMA) were proposed as alternative MRAM writing mechanisms. SOT is able to switch the FL of a pMTJ by injecting an in-plane current in an adjacent SOT layer, which enables a three-terminal cell structure with energy-efficient and reliable sub-ns writing capabilities [3]. On the other hand, VCMA promises significant advances toward low-power MRAM. The electronic-based VCMA effect can instantly modify the perpendicular magnetic anisotropy (PMA) of the FL to induce precessional switching at GHz rates and ultra-low energy consumption (fJ) [4]. However, both mechanisms also present technological challenges. The challenges for SOT are currently related to the density and write efficiency: the 2-transistor 1-MTJ cell structure limits the array density, and the SOT write current remains larger than for STT-MRAM, which imposes a large selector transistor to accommodate its write current. For VCMA, the write margin is small, and is subject to the variations in VCMA coefficient and field amplitudes, making write control difficult in dense arrays. Further, a large VCMA effect (>1000fJ/Vm) is mandatory to avoid compromising retention in sub-30nm pMTJ, which remains as a major challenge as typical values in pMTJs are 30-60 fJ/Vm at device level [5]. To overcome the above-cited limitations and to combine the best of these two approaches, voltage-gate assisted spin-orbit torque (VGSOT)-MRAM concept [Fig. 1(a)] has been proposed [6]. In this work, we report on VGSOT switching properties in pMTJ, integrated with our 300mm SOT-MRAM platform [3]. The stack is composed of W(3.5nm)/CoFeB(1nm)/MgO(1.7nm, RA ~ 5kΩ.μm2)/RL/SAF, where the thick MgO ensures pure VCMA gate control without STT contribution. We use an electrical scheme that allows for individual control over SOT/gate pulse amplitudes (VSOT/Vg), and variable pulse duration (tp). Fig. 1(b) shows exemplary SOT switching probability (Psw) curves under different Vg, at tp = 0.4ns. We observe a clear decrease (increase) in VSOT under Vg of 1V (-1V) for both AP-P and P-AP transitions. The critical switching voltage, defined at Psw = 50%, is converted into the critical switching current (Ic) and plotted as a function of 1/tp in Fig. 1(c). It shows a typical linear scaling, i.e. Ic = Ic0 + q/tp in the sub-ns regime for all gate values [7], where Ic0 is the intrinsic critical current and q indicates the nucleation energy for magnetization reversal. The linear dependences of Ic0 and q on Vg [Fig. 1(d)] reflect the direct modification of PMA upon Vg applications and the change of nucleation energy, respectively. We report here a 25% reduction in Ic under Vg = 1V, which corresponds to a 45% reduction in total switching energy to 30fJ at 0.4ns. We further demonstrate that VGSOT offers reliable sub-ns switching with a low write error rate (<10-5) and that VGOST-pMTJ is highly durable against large read/write stresses (>1012) Finally, we benchmark the VGSOT performance at the 5nm technology node against other embedded memory technologies to highlight the VGSOT benefits. It reveals that VGSOT-4MTJ design can reduce the effective cell area to <0.5x of the high-density SRAM at minimal performance degradation. Meanwhile, the constrain of achieving challenging material parameters for VCMA-MTJ (ξ > 1000fJ/Vm) and SOT-MTJ (θSH > 1.5) can be relaxed to reasonable values: ξ = 300fJ/Vm and θSH = 0.45. Our study shows the great potential of this VGSOT approach for fast, dense and low power embedded memory applications. **