This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM.