A novel read decoupled 8T1M nvSRAM cell for near threshold operation

Abstract

The SRAM is mainstay in on-chip memories due to easier integration with standard processing technology and high performance. The SRAM cell is required to have the reliable performance of at strong inversion region as well as near threshold region. The performance of the SRAM cell degrades near threshold voltage due to the increase in the susceptibility to the noise. Also, the idle cells in the SRAM array consume power which is undesirable. A new nvSRAM cell is introduced in this paper which can maintain its performance near threshold voltage. The power consumption is reduced up to 99.7% during write ‘1’ operation. Also, the writability is improved by 69% in comparison to the existing counterparts. The store/restore delay and energy are improved by 70% and 47% respectively. The simulations are carried out using PTM model of 32 nm PTM model of CMOS technology node for different supply voltage. The simulations at different technology node are also carried out to validate the results.