Abstract
This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.
Highlights
M ONOLITHIC 3-D (M3D) integrated circuits (ICs) using fine-grain nanoscale interlayer vias (ILVs) promise significant energy-efficiency improvements over 2-D ICs [1]
We present an SRAM compiler for CNFET-M3D using the process design kit (PDK) developed by Srimani et al [2]
We demonstrate the application of the CNFET M3D SRAM compiler for generating SRAM subarrays, blocks, and arrays of varying capacities
Summary
M ONOLITHIC 3-D (M3D) integrated circuits (ICs) using fine-grain nanoscale interlayer vias (ILVs) promise significant energy-efficiency improvements over 2-D ICs [1]. The need for high-temperature processing of silicon-based MOSFET (1000 ◦C) during sequential fabrication of one tier can degrade the reliability and performance of devices in previously fabricated tiers [1]–[5]. Carbon nanotube FET-based M3D process has emerged as an attractive alternative to the silicon-based M3D process [2], [4], [8]–[11]. This is because CNFET can be fabricated at the temperature below 425 ◦C, which eliminates potential defects of devices and interconnections on previously fabricated tiers [2]. CNFET promises high energy efficiency in designing logic and memory circuits [8], [9]. Srimani et al [2] have demonstrated commercial-grade M3D process design kits (PDKs) and the operation of logic and SRAM
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