Spin Transfer Torque Magnetic Random Access Memory Research Articles

Experimental analysis on stochastic behavior of preswitching time in STT-MRAM

In this paper we present an experimental study on the preswitching time of Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) with a resistance area R.A. ~ 12 Ω.μm2, for both transitions, Anti-Parallel to Parallel state and vice versa. A set of measurements is carried out operating at different applied voltages and temperatures ranging from 25 °C to 90 °C. As main results of our analysis, we show the decrease of the preswitching time with temperature increase. The Arrhenius law enables the extraction of the activation energy required to switch the cell in both states. Finally, we establish the relevant state transition probabilities using the Weibull distribution that best fits our results. The Weibull parameters highlight the preswitching time stochasticity and the variability of the switching characteristics of the STT-MRAM device, useful in high reliability applications.

Fast Writing Strategy of STT-MRAM With Pipeline Architecture

A fast writing strategy of spin transfer torque (STT) magnetic random access memory (STT-MRAM) combined with pipeline architecture and early write termination (EWT) technology is proposed in this article. Both the writing speed and the writing power consumption of STT-MRAM are optimized. First, based on the proposed pipeline structure, the writing operation can be conducted within a single clock cycle, much decreasing the writing time. Second, the EWT technology is adopted in the writing operation. In the traditional operation of STT-MRAM, the same data are repeatedly written to the memory cell, which wastes the writing power consumption and the writing operation time. In this article, combined with the EWT technology and the pipeline architecture, the unnecessary writing power is reduced by 92.8%, while the necessary writing power is increased by 19.8%. Taking 32 kb data for the writing operation, the operation speed of the new writing strategy is increased by 67.4% compared with the incumbent writing technology. The proposed strategy has potential application in the embedded STT-MRAM acting as cache memory in the computer system.

Nanoscale Thermal Transport Model of Magnetic Tunnel Junction (MTJ) Device for STT-MRAM

Spin-transfer-torque magnetic random access memory (STT-MRAM) based on magnetic tunnel junction (MTJ) device has attracted significant attention from academics and industries. Nevertheless, the thermal effect under bias operation affects the overall performance and stability of a device. To evaluate the thermal phenomenon in MTJ devices accurately, the non-equilibrium effect between the electron and the phonon near the electrode-barrier interface cannot be ignored. The existence of the interface leads to additional thermal resistance hindering the heat conduction of tunnel junction. Therefore, an effective equivalent model concerning the interface effect is necessary to represent the heat transportation of the device. In this article, a nanoscale thermal transport model of the MTJ device is proposed. The influence of the thermal conductivity of the nano-oxide layer on the temperature distribution is discussed. The interface energy balance transport model is used to clarify the non-equilibrium relationship between the phonon and the electron at the CoFeB/MgO/CoFeB interfaces. A parameterization study is conducted to illustrate the temperature distribution in the nanoscale thermal transport model. Furthermore, the phonon-electron coupling distance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta$ </tex-math></inline-formula> ) based on the thermal conductivity of the phonon ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa _{p}$ </tex-math></inline-formula> ) and the electron ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa _{e}$ </tex-math></inline-formula> ) of the device is implemented to construct the effective equivalent model using finite element modeling (FEM), which could realistically reflect the thermal transport under working conditions. The established equivalent model has a guiding role in exploring the thermal transportation in the nanoscale MTJ device.

Design of LUT-Based LDPC Decoders for Spin-Transfer Torque Magnetic Random Access Memory

Recently, low-density parity-check (LDPC) codes have been proposed to improve the reliability of spin-transfer torque magnetic random access memory (STT-MRAM). While several research works focus on the design of LDPC codes to combat the process variation and thermal fluctuation of the STT-MRAM, we aim to tackle the high decoding latency issues by the novel design of a lookup table (LUT)-based LDPC decoder for the forward and backward (FB) processes. In this work, the channel quantizer and LUT operations of the LDPC decoder are jointly designed by minimizing the error probability estimated from the density evolution (DE) algorithm. The simulation results show that the proposed design method for a code rate of 0.9 outperforms the previous methods in terms of bit error rate (BER) performance. Furthermore, the proposed design can support the channel model of the STT-MRAM without an independent and identically distributed (i.i.d.) channel adapter.

Field-Free Spin-Orbit Torque Switching Enabled by the Interlayer Dzyaloshinskii-Moriya Interaction.

Perpendicularly magnetized structures that are switchable using a spin current under field-free conditions can potentially be applied in spin-orbit torque magnetic random-access memory (SOT-MRAM). Several structures have been developed; however, new structures with a simple stack structure and MRAM compatibility are urgently needed. Herein, a typical structure in a perpendicular spin-transfer torque MRAM, the Pt/Co multilayer and its synthetic antiferromagnetic counterpart with perpendicular magnetic anisotropy, was observed to possess an intrinsic interlayer chiral interaction between neighboring magnetic layers, namely, the interlayer Dzyaloshinskii-Moriya interaction (DMI) effect. Furthermore, using a current parallel to the eigenvector of the interlayer DMI, we switched the perpendicular magnetization of both structures without a magnetic field, owing to the additional symmetry breaking introduced by the interlayer DMI. This SOT switching scheme realized in the Pt/Co multilayer and its synthetic antiferromagnet structure may open a new avenue toward practical perpendicular SOT-MRAM and other SOT devices.

CRP: Conditional Replacement Policy for Reliability Enhancement of STT-MRAM Caches

Driven by the trends of emerging technologies in on-chip memories, with increasing the size of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT-MRAMs) are the most promising alternative technology among the non-volatile memories (NVMs) to replace SRAMs. Despite their high density, scalability, and near-zero leakage power, the reliability of STT-MRAM LLCs is threatened by a high error rate due to their stochastic switching behavior. The error rate is highly influenced by the cache management, which necessitates redesigning the cache replacement policy based on the error behavior. In this article, we propose an error-aware cache replacement policy, namely, conditional replacement policy (CRP), to improve the reliability of STT-MRAM caches by decreasing the rate of both read disturbance and write failure. This is ascertained by nominating an appropriate data block in the cache to be replaced with an incoming data block, considering the minimum error rate. Moreover, the performance and latency of both write and read operations are considered. The simulation results show that compared with the state-of-the-art replacement policy in STT-MRAM caches, CRP reduces the total error rate by 68%. In addition, the proposed policy enhances the performance by 2% and saves energy consumption by 19%, on average. Meanwhile, the total number of writes is decreased by 41% compared with the previous scheme.

Two-dimensional materials prospects for non-volatile spintronic memories.

Non-volatile magnetic random-access memories (MRAMs), such as spin-transfer torque MRAM and next-generation spin-orbit torque MRAM, are emerging as key to enabling low-power technologies, which are expected to spread over large markets from embedded memories to the Internet of Things. Concurrently, the development and performances of devices based on two-dimensional van der Waals heterostructures bring ultracompact multilayer compounds with unprecedented material-engineering capabilities. Here we provide an overview of the current developments and challenges in regardto MRAM, and then outline the opportunities that can arise by incorporating two-dimensional material technologies. We highlight the fundamental properties of atomically smooth interfaces, the reduced material intermixing, the crystal symmetries and the proximity effects as the key drivers for possible disruptive improvements for MRAM at advanced technology nodes.

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5.67 × 10−4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 × 10−3.

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near-memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro using a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunction with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR–based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps.

Off-axis electron holography for the direct visualization of perpendicular shape anisotropy in nanoscale 3D magnetic random-access-memory devices

Perpendicular shape anisotropy (PSA) and double magnetic tunnel junctions (DMTJs) offer practical solutions to downscale spin-transfer-torque Magnetic Random-Access Memory (STT-MRAM) beyond 20 nm technology nodes, while retaining their thermal stability and reducing critical currents applied. However, as these modern devices become smaller and three-dimensionally (3D) complex, our understanding of their functional magnetic behavior is often indirect, relying on magnetoresistance measurements and micromagnetic modeling. In this paper, we review recent work that was performed on these structures using a range of advanced electron microscopy techniques, focusing on aspects specific to the 3D and nanoscale nature of such elements. We present the methodology for the systematic transfer of individual SST-MRAM nano-pillars from large-scale arrays to image their magnetic configurations directly using off-axis electron holography. We show that improved phase sensitivity through stacking of electron holograms can be used to image subtle variations in DMTJs and the thermal stability of &amp;lt;20 nm PSA-STT-MRAM nano-pillars during in situ heating. The experimental practicalities, benefits, and limits of using electron holography for the analysis of MRAM devices are discussed, unlocking practical pathways for direct imaging of the functional magnetic performance of these systems with high spatial resolution and sensitivity.

Unveiling Temperature-Dependence Mechanisms of Perpendicular Magnetic Anisotropy at Fe / MgO Interfaces

The perpendicular magnetic anisotropy (PMA) at magnetic transition metal/oxide interfaces is a key element in building out-of-plane magnetized magnetic tunnel junctions for spin-transfer-torque magnetic random access memory (STT-MRAM). Size downscaling renders magnetic properties more sensitive to thermal effects. Thus, understanding the temperature dependence of the magnetic anisotropy is crucial. In this work, we theoretically address the correlation between temperature dependence of PMA and magnetization in typical Fe/MgO-based structures. In particular, the possible mechanisms behind the experiments reporting deviations from the Callen and Callen scaling power law are analyzed. At ideal interfaces, first-principles calculations reveal (i) small high-order anisotropy constants compared to first order and (ii) enhanced exchange constants. Considering these two intrinsic effects in the atomistic simulations, the temperature-dependence of the total and layer-resolved anisotropy are found to follow the Callen and Callen scaling power law, thus ruling out an intrinsic microscopic mechanism underlying deviations from this law. Besides, two possible extrinsic macroscopic mechanisms are unveiled namely the influence of the dead layer, often present in the storage layer of STT-MRAM cells, and the spatial inhomogeneities of the interfacial magnetic anisotropy. About the first mechanism, we show that the presence of a dead layer tends to reduce the scaling exponents. In the second mechanism, increasing the percentage of inhomogeneity in the interfacial PMA is revealed to decrease the scaling exponent. These results allow us to explain the difference in scaling exponents relating anisotropy and magnetization thermal variations reported in earlier experiments. This is crucial for the understanding of the thermal stability of the storage layer magnetization in STT-MRAM applications.

Differential spin Hall MRAM based low power logic circuits and multipliers

A Multiplier is an essential component that dictates the performance of modern computing systems. However, high power dissipation of complementary metal-oxide semiconductor (CMOS) multiplier circuits has become a major concern in sub 45 nm technology nodes. Recently, emerging non-volatile memory based hybrid circuits have gained a lot of attention due to the prominent feature of negligible static power consumption. Magnetic tunnel junction (MTJ) based spin-torque memories have been used for low power applications. However, spin-transfer torque magnetic random-access memory (STT-MRAM) based hybrid CMOS/MTJ circuits exhibit higher write energy and longer incubation delay. In this work, a differential spin Hall (DSH)-MRAM cell is employed for logic and circuit applications. It stores a pair of complementary bits with low write voltage and reduced area. The variability analysis of DSH-MRAM signifies the availability of sufficient margin between different resistance states. Different types of 8 × 8 and 4 × 4 hybrid CMOS/MTJ multipliers are analyzed using DSH based adders and logic gates. The proposed multipliers consume approximately 20% less power and exhibit 19% improvement in power-delay product characteristics compared to CMOS based multipliers.

Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs

This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (−56% and −37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures.

STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment

The demand for high-performance computing and rapidly increasing power consumption has increased the necessity for application-specific accelerators. In the datacenter and mobile system, more applications are increasingly relying on accelerators. Field-programmable gate arrays (FPGAs) emerge as a good candidate because they have high programmability and power efficiency. As the number of applications requiring acceleration increases, there is huge demand for FPGAs that support multiple contexts. Previous FPGA designs that support multicontext have various shortcomings such as volatility, poor power efficiency, large performance, area, and reconfiguration overhead. In this article, we propose a spin-transfer torque magnetic RAM (STT-MRAM)-based nonvolatile multicontext FPGA (NVMC-FPGA) that overcomes these shortcomings. We introduce the NVMC-FPGA architecture and operation modes that take advantage of nonvolatility and support multicontext. We also develop the multicontext-aware FPGA computer aided design flow to make the most of the NVMC-FPGA. Compared to the conventional SRAM-based FPGA, when eight identical circuits are mapped, the NVMC-FPGA improves the performance by 15.3% on average and reduces the power consumption by 11.2%–80.7%, depending on the number of simultaneously activated circuits. Moreover, when eight different circuits are mapped, the NVMC-FPGA improves the performance by 58.5% on average and reduces the power consumption by 6.2%–63.3%, depending on the number of simultaneously activated circuits.

Seebeck effect and Joule heating in CoFeB/MgO/CoFeB-based perpendicular magnetic tunnel junctions with low resistance area product

Perpendicular magnetic tunnel junctions (p-MTJs) have attracted great interest due to their excellent performance in spin-transfer-torque magnetic random access memories (STT-MRAMs). Here, the resistance states can be manipulated by an applied current in the order of 109–1010 A m−2, yet the appearance of a heating influence must be understood. In this work, we systematically study the Seebeck effect in nano scale p-MTJs induced due to Joule heating by the tunneling current. The CoFeB/MgO/CoFeB-based p-MTJs were nanofabricated and the current-induced switching was characterized. We find a sign change of the thermovoltage (ΔV) between AP (positive) and P (negative) states, indicating a significant dependence of the Seebeck effect on the magnetic state of the p-MTJ. The temperature distribution in the stack was simulated, by which the Seebeck coefficient (S) and the tunnel magneto-Seebeck ratio were calculated. Our further study indicates that the thermal STT can reduce the switching currents, showing the possibility to re-use this dissipative heating energy. To improve the efficiency of the energy re-use, a method is proposed through the materials optimization of the non-magnetic layers but still retaining high tunneling magnetoresistance effect. Our study shows that the magneto-Seebeck effect plays an important role in the p-MTJs, which can be crucial and must be considered in the design of the high performance p-STT-MRAMs and thermal-assisted MRAMs.

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

In-memory computing (IMC) is an effective solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with an analog-to-digital converter (ADC) and simultaneously completes the calculation of multi-line data with a high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns including low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. The TMR is magnified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7500\times $ </tex-math></inline-formula> using a latch structure in combination with the device. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with a feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-and-accumulate (MAC) computations simultaneously. The proposal is simulated using the 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN).

Comparative analysis of STT and SOT based MRAMs for last level caches

In recent years, magnetic RAMs have stimulated considerable research interest due to its high area-density and low leakage-power with comparable speed that makes it a strong contender for possible replacement of conventional RAMs. However, the operational speed of MRAM is relatively lower than the SRAMs. Advanced switching mechanism such as Spin Transfer Torque (STT), Voltage-Controlled Magnetic Anisotropy (VCMA), Magneto Electric (ME) effect, and Spin-Orbit Torque (SOT) has been introduced to further improve the speed of operation. This paper explores the comparative analysis of STT and SOT-based MRAMs for the application of Large Last-Level Caches (L3Cs). It will give an insight into the MRAM from device to architectural level, in-aspect of performance parameters such as read-write energy consumption, leakage power, chip-area and read-write latency. This research work is carried out through a benchmarked simulation framework, starting from device to architectural level. At the cell level, it is observed that STT-MRAM takes 50% less area with 74% reduction in leakage power dissipation as compared to SOT-MRAM. However, the SOT-MRAMs is 4× faster than the STT-MRAM. At the architectural level, SOT-MRAM outperforms STT-MRAM in terms of read/ write energy and latency at the cost of marginal chip-area and leakage-power. Overall, in comparison to its conventional counterpart (SRAMs), SOT MRAMs are proved to be a superior candidate at a large size of LLCs in all aspects.

Union Bound Analysis for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) With Channel Quantization

As an emerging non-volatile memory (NVM) technology, spin-torque transfer magnetic random access memory (STT-MRAM) has received great attention in recent years since it combines the features of low switching energy, fast write/read speed, and high scalability. However, process variation and thermal fluctuation severely affect the data integrity of STT-MRAM, resulting in both write errors and read errors. Therefore, effective error correction codes (ECCs) are necessary for correcting memory cell errors. Meanwhile, the design of channel quantizer plays a critical role in supporting error correction coding for STT-MRAM. In this work, we propose a union bound analysis which can accurately predict the word error rates (WERs) of ECCs with maximum-likelihood (ML) decoding over the quantized STT-MRAM channel. The derived bound provides a theoretical tool for comparing the performance of ECCs with different quantization schemes at very low error rate levels without resorting to lengthy computer simulations. Moreover, we also propose a new criterion to design the channel quantizer by minimizing the WERs of ECC decoding that are obtained from the union bound analysis. Numerical results show that the proposed union-bound-optimized (UBO) quantizer can achieve better error rate performance than the state-of-art quantizers for STT-MRAM.

Perspectives on spintronics technology development: Giant magnetoresistance to spin transfer torque magnetic random access memory

The discovery of the giant magnetoresistance (GMR) effect in 1988 started a new field called spintronics and was recognized with the 2007 Nobel Prize in Physics, which was awarded to Fert and Grunberg. Spintronics is based on the contribution of both electron spin and electron charges of materials to facilitate electronic functions, enabling one extra degree of freedom for device operations. Spintronics has grown rapidly during the past three decades with significant discoveries, technological advancements, and material and device developments that have led to numerous product applications. Furthermore, new research fields and technology areas have been discovered and continue to expand. In this Perspective, key technological advances in the field during the past three decades will be highlighted, starting with the developments that led to the first use of the GMR effect in hard disk drives and its impact in the spintronic ecosystem to currently used perpendicular magnetic tunnel junctions (pMTJs) for spin transfer torque magnetic random access memory (STT-MRAM) devices. The important aspects of the pMTJ characteristics for the application of STT-MRAM will be discussed. This Perspective will present perspectives on a new structure that enhances the efficiency of the pMTJ-based STT-MRAM and research directions that can drive further advances in spintronics.

Influence of ferromagnetic layer thickness on the Gilbert damping and magnetocrystalline anisotropy in PLD grown epitaxial Co2FeSi Heusler alloy thin films

In the present work, full Heusler alloy (FHA) Co2FeSi (CFS) epitaxial thin films with thickness (tCFS) ranging from 5–25 nm were grown by Pulse laser deposition (PLD) on MgO (001) substrates at an optimized deposition temperature of 600°C. Dynamic magnetization response of PLD-grown CFS thin films was systematically investigated as a function of tCFS. Thickness-dependent structural and magnetic correlation exhibit a non-monotonic variation in Gilbert damping parameter, α. The ferromagnetic resonance (FMR) investigation revealed that the presence of lattice strain and a lower degree of atomic ordering in the thinner FHA CFS films, results in additional enhancement of α. The lowest α value of 4×10−3 is obtained from the theoretical fit of experimental data in a 20 nm thick film. This low value of α is suitable in magnonic devices, such as spin-transfer torque magnetic random-access memories (STT-MRAMs) where an efficient spin injecting source from a FHA ferromagnet to a non-magnetic interface is required. Further, in-plane angle-dependent (φ-variation) FMR measurements of the sample yield an intrinsic four-fold magnetocrystalline anisotropy (MCA) along with the presence of uniaxial anisotropy that has non-monotonicity with tCFS. A significant value of cubic anisotropy constant of 5.16×105erg/cm3 has been obtained in the film with a thickness of around 15nm. Further investigation suggests that uniaxial anisotropy in the CFS/MgO film is a combination of strain-induced magneto-elastic and interface-related contribution that is intrinsic in nature. The experimental observations have been verified by using micromagnetic simulations run on the epitaxial crystal structure. FMR mode position and linewidth of varied thickness CFS films are generated by micromagnetic simulations utilizing the Landau–Lifshitz–Gilbert formalism.