Comparative analysis of STT and SOT based MRAMs for last level caches

Abstract

In recent years, magnetic RAMs have stimulated considerable research interest due to its high area-density and low leakage-power with comparable speed that makes it a strong contender for possible replacement of conventional RAMs. However, the operational speed of MRAM is relatively lower than the SRAMs. Advanced switching mechanism such as Spin Transfer Torque (STT), Voltage-Controlled Magnetic Anisotropy (VCMA), Magneto Electric (ME) effect, and Spin-Orbit Torque (SOT) has been introduced to further improve the speed of operation. This paper explores the comparative analysis of STT and SOT-based MRAMs for the application of Large Last-Level Caches (L3Cs). It will give an insight into the MRAM from device to architectural level, in-aspect of performance parameters such as read-write energy consumption, leakage power, chip-area and read-write latency. This research work is carried out through a benchmarked simulation framework, starting from device to architectural level. At the cell level, it is observed that STT-MRAM takes 50% less area with 74% reduction in leakage power dissipation as compared to SOT-MRAM. However, the SOT-MRAMs is 4× faster than the STT-MRAM. At the architectural level, SOT-MRAM outperforms STT-MRAM in terms of read/ write energy and latency at the cost of marginal chip-area and leakage-power. Overall, in comparison to its conventional counterpart (SRAMs), SOT MRAMs are proved to be a superior candidate at a large size of LLCs in all aspects.