Fast Writing Strategy of STT-MRAM With Pipeline Architecture

Abstract

A fast writing strategy of spin transfer torque (STT) magnetic random access memory (STT-MRAM) combined with pipeline architecture and early write termination (EWT) technology is proposed in this article. Both the writing speed and the writing power consumption of STT-MRAM are optimized. First, based on the proposed pipeline structure, the writing operation can be conducted within a single clock cycle, much decreasing the writing time. Second, the EWT technology is adopted in the writing operation. In the traditional operation of STT-MRAM, the same data are repeatedly written to the memory cell, which wastes the writing power consumption and the writing operation time. In this article, combined with the EWT technology and the pipeline architecture, the unnecessary writing power is reduced by 92.8%, while the necessary writing power is increased by 19.8%. Taking 32 kb data for the writing operation, the operation speed of the new writing strategy is increased by 67.4% compared with the incumbent writing technology. The proposed strategy has potential application in the embedded STT-MRAM acting as cache memory in the computer system.