Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory

Abstract

The dependence of the write-error rate (WER) on the applied write voltage, write pulse width, and device size was examined in individual devices of a spin-transfer torque (STT) magnetic random-access memory (MRAM) 4 kbit chip. We present 10 ns switching data at the ${10^{ - 6}}$ error level for 655 devices, ranging in diameter from 50 nm to 11 nm, to make a statistically significant demonstration that a specific magnetic tunnel junction stack with perpendicular magnetic anisotropy is capable of delivering good write performance in junction diameters range from 50 to 11 nm. Furthermore, write-error-rate data on one 11 nm device down to an error rate of $7{\times}10^{ - 10}$ was demonstrated at 10 ns with a write current of $7.5\;\upmu{\rm A}$ , corresponding to a record low switching energy below 100 fJ.