SPICE Tool Research Articles

Global RC Interconnects with ADL Buffers for Low-Power Applications

Introduction: Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem. Methods: With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL). Results: To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit. Conclusion: The suggested model's performance is compared to that of other cutting-edge methods.

ReARTSim: an ReRAM ARray Transient Simulator with GPU optimized runtime acceleration

The demand for computation driven by machine learning and deep learning applications has experienced exponential growth over the past five years (Sevilla et al 2022 2022 International Joint Conference on Neural Networks (IJCNN) (IEEE) pp 1-8), leading to a significant surge in computing hardware products. Meanwhile, this rapid increase has exacerbated the memory wall bottleneck within mainstream Von Neumann architectures (Hennessy and Patterson et al 2011 Computer architecture: a quantitative approach (Elsevier)). For instance, NVIDIA graphical processing units (GPUs) have gained nearly a 200x increase in fp32 computing power, transitioning from P100 to H100 in the last five years (NVIDIA Tesla P100 2023 (www.nvidia.com/en-us/data-center/tesla-p100/); NVIDIA H100 Tensor Core GPU 2023 (www.nvidia.com/en-us/data-center/h100/)), accompanied by a mere 8x scaling in memory bandwidth. Addressing the need to mitigate data movement challenges, process-in-memory designs, especially resistive random-access memory (ReRAM)-based solutions, have emerged as compelling candidates (Verma et al 2019 IEEE Solid-State Circuits Mag. 11 43–55; Sze et al 2017 Proc. IEEE 105 2295–329). However, this shift in hardware design poses distinct challenges at the design phase, given the limitations of existing hardware design tools. Popular design tools today can be used to characterize analog behavior via SPICE tools (PrimeSim HSPICE 2023 (www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html)), system and logical behavior using Verilog tools (VCS 2023 (www.synopsys.com/verification/simulation/vcs.html)), and mixed signal behavior through toolbox like CPPSIM (Meninger 2023 (www.cppsim.org/Tutorials/wideband_fracn_tutorial.pdf)). Nonetheless, the design of in-memory computing systems, especially those involving non-CMOS devices, presents a unique need for characterizing mixed-signal computing behavior across a large number of cells within a memory bank. This requirement falls beyond the scope of conventional design tools. In this paper, we bridge this gap by introducing the ReARTSim framework—a GPU-accelerated mixed-signal transient simulator for analyzing ReRAM crossbar array. This tool facilitates the characterization of analog circuit and device behavior on a large scale, while also providing enhanced simulation performance for complex algorithm analysis, sign-off, and verification.

High Speed and Low Leakage Power Voltage Level Shifter using Regulated Cross-Coupled Network

This concise presents a power efficient level shifter using regulated cross-coupled network with split inverter. With the use of regulated cross-coupled network, power dissipation of the pull-up region drastically decreases. Level shifters convert the voltage levels which are below the threshold voltage to the acceptable voltage levels by decreasing the transistor size. A Split inverter is used at the output to decrease the short circuit current. Modified Split inverter along with the load capacitor at the output is used to increase the speed and to decrease the power consumption. This LS can save 31% power compared to other techniques. The proposed level shifter works effectively at high speed and consumes less power. For simulation, LT spice tool of 50 nm technology and 90 nm technology is used.

Design and Performance Analysis of Ultra-Wide Bandgap Power Devices-Based EV Fast Charger Using Bi-Directional Power Converters

A widespread introduction of electric vehicles would require an advanced enriched fast-charging infrastructure and battery technology. Currently used silicon (Si) based power electronic devices limit their efficiencies, power density, and switching frequency. Designing fast-charging stations using these materials is not suitable due to low breakdown potential, less thermal stability, and less power handling abilities. The research will propose an off-board DC high-power density fast charging infrastructure with grid tie application. The EV station is designed by using ultra-wideband gap (UWBG) material-based power electronic devices to charge the EV vehicles in a few minutes up to an acceptable state of charge. The study will analyze the characteristics of Gallium III oxide (Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) material power devices by modeling them using SPICE and TCAD software tools. The research presents the Simscape physical modeling of electric vehicle chargers based on Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> power devices. Design analysis of three-phase bidirectional AC/DC converter and DC/DC isolated full bridge converter is present in this paper. Research implements the unity power factor control to improve the power quality requirements of the power grid. The dual active power control of converters provides a wide range of charging power for a variety of EV batteries. The study will provide high current and reliable rapid charging for currently available and upcoming future electric vehicles.

Design and Performance Analysis of High-Performance Low Power Voltage Mode Sense Amplifier for Static RAM

In the prominent era of the digital world and Very Large-Scale Integration (VLSI) circuits, Static Random Access Memory (SRAM) provides a vital contribution to low-power and high-speed performance. Sense Amplifiers (SA) are a part of Complementary Metal-Oxide-Semiconductor (CMOS) memories used to read the stored information. This paper indicates a Dual-Voltage, Dual-Tail Level Restoration Voltage Latch Sense Amplifier (DVDTLR-VLSA). The design has been implemented using the LT SPICE tool at 180nm technology node with a 1.8V supply. Performance comparison of existing SA presented in literature with the proposed SA is examined based on different parameters like power, energy, delay, and current. The proposed design maintains power at 2.167uW that is decreased to half as against Dual Switch Transmission Gate Voltage SA (DTGVSA) and shows an appreciable depletion. Also, the current and delay results are improved. Dimensional analysis is also done for the proposed SA to examine the performance. After that, the effect of sleep transistors on the proposed SA examines the performance in comparison to delay and power parameters without sleep transistors. The DVDTLR-VLSA has minimal energy and power. Also, the delay is improved which may be determined more advisable for low-power operations.

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic

Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

P‐117: AI Analysis of HOP Circuit Failure and Improvement

AMOLED's HOP(hybrid of Oxide semiconductor and Polysilicon TFT) technology was born to meet the market's demand for low power consumption. Also, the IGZO oxide process was introduced with new driving technology to support the low driving frequency operation. However, this new GC circuit of oxide TFT driving caused new and randomly appearing horizontal defects which do not exist in LTPS circuits. To solve this issue, we studied to find the design parameters using pipelined deep learning models composed of CGAN(Conditional Generative Adversarial Network), VGM(Variational Gaussian Mixture), and XAI(eXplainable Artificial intelligence) technologies to figure out what causes these defects. We collected HOP panel design information to achieve the given goal and confirmed the degree of defect per HOP model. Since the number of HOP models is limited, XAI analysis might also be negligible. We solve this issue by generating data using CGAN and VGM in sequence. After, ALE(Accumulated Local Effects), a popular XAI technique, is applied to find affected design parameters and change‐related circuit designs to help verify the proposed algorithm's performance. As a result of this design change, we identified that the related defect rate decreases from 15000ppm to less than 500 ppm, in which XAI plays a significant role in solving a newly introduced defect issue. That was believed for a long time a challenging problem to analyze using the legacy SPICE tool in the OLED circuit field. Our result also suggests that even predicting the defect rate of future HOP models becomes feasible with our proposed deep learning architecture.

Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

For the analysis of the characteristics and behavior of circuits prior to fabrication and to improve circuit performance, simulations using Spice tools are typically performed. Such tools rely on static compact models describing the behavior of the individual circuit components such as transistors. In reality, the behavior of the transistors changes over time due to aging, for instance, as a consequence of bias temperature instabilities (BTI). BTI is typically referred to as a drift of the threshold voltage of a transistor due to charge trapping at oxide and interface defects. To explain BTI, power-law-like mathematical expressions are often employed. However, using these simple formulas, the experimental data can only be replicated with limited accuracy. To evaluate the performance of logic inverter circuits made from 4H-SiC CMOS transistors with high precision, we use a physics-based defect model to describe the change of the device behavior from a defect-centric perspective. Our results indicate the limitations of using power-law-like formulas as they lead to an overly pessimistic estimation for circuit parameters.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply

This work presents two new CMOS designs of current mode squarer circuits using a 1.5 V supply. The four-quadrant multiplier has also been designed using proposed squarer circuits. To improve bandwidth, the resistive compensation scheme has been exploited. The input and output signals of proposed circuits are of current type and hence exhibit larger dynamic range contrary to voltage mode circuits. Various simulations have been carried out to check performance and validate theoretical analysis. It is observed that range of − 3 dB bandwidth, power consumption and linearity error of the proposed circuits I and II are 542.53 MHz and 1.13 GHz, 0.56 and 0.47 mW and 1.8 and 2%, respectively. In the state of the art, it is noticed that around 10–90% bandwidth is increased while using proposed circuits over most of the conventional circuits. All results are verified using spice tools and 0.18 µm CMOS technology parameters.

The design and simulation of a MOSFET-based MEMS pressure sensor using an integrated simulation approach

A novel integrated design and simulation approach is applied to analyze the performance of a metal–oxide–semiconductor field-effect transistor (MOSFET)-based microelectromechanical systems (MEMS) pressure sensor circuit while varying circuit and CMOS parameters, viz. the supply voltage and threshold voltage (Vt), respectively. For effective mechanical pressure sensing, a sensor MOSFET is integrated near the fixed edge of a deformable silicon diaphragm for maximum stress exposure. The stress value where the sensor MOSFET is located on the diaphragm surface is calculated using the finite-element method (FEM). Additionally, the threshold voltage required to activate the sensor MOSFET is also extracted using the FEM. The extracted value of Vt along with the corresponding gate oxide thickness are used to design and simulate the sensor circuit in the SPICE tool. The FEM-based multiphysics simulation is linked to a standard direct-current (DC) model SPICE simulation using our proposed carrier mobility model for a MOSFET under mechanical stress. All the FEM computations are performed using COMSOL Multiphysics, all the electrical simulations are performed using LT-SPICE, and the full sensor circuit is designed and simulated by integrating COMSOL Multiphysics and LT-SPICE via a MATLAB script. The validity of the design is confirmed by comparing these results with analytical computations. The results obtained using the integrated simulation approach confirm that the design is reliable and enable the sensor performance to be examined in terms of its sensitivity, yielding a value of 30 mV/MPa.

Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization

The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.

Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects

Rigorous technology scaling of integrated circuits to nanometer range aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based carbon nanotube bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such bundle configurations boost the performance of system in terms of reducing system latency and power consumption in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22 nm technology node.

The Involution Tool for Accurate Digital Timing and Power Analysis

We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping.We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates.

A Novel Approach for Analysis CNTFET Based Domino circuit in Nano-Scale Design

As semiconductor industries is developing day by day to meet the requirement of today’s world. As scaling of ICs day by day to introduce functionality of the device while fabrication more and more component which results in shorter the life of the battery operated device which has to be improved. Here in this article we have measured performance parameters like power consumption, UNG, Evaluation Delay, standby power and speed of various domino circuits provided for various inputs like 8 &amp;16 input OR gate. When we compared power, delay, and PDP of different topologies of domino circuit design with the simulation results which is performed by using SPICE tool at 32nm CNTFET process technology with supply voltage 0.9V and 27⁰ C of temperature at 100 MHz. All the simulation results is done in CMOS &amp; CNTFET technology, it is observed that saving of average power upto 90.46% with same delay, with improvement of 5.8 × Noise-immunity with scaling of technology.

A high gain and high bandwidth three stage amplifier using FGMOS and 0.5 V dual supply

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

Reduction of leakage power and vulnerability to radiation are of critical challenges in modern nanometer CMOS technologies because of scaling down requirement. Spintronic logic has been progressed to realize these demands based on magnetic-based elements properties especially magnetic tunnel junction (MTJ) such as radiation-hardened, non-volatility, and CMOS process compatibility. A novel soft-error tolerant and highly reliable latch circuit is proposed in this paper which is a promising choice for reliable and low-power architectures. Furthermore, employing the proposed shadow latch based on MTJ cells as a backup structure along with the rad-hard main latch is aimed to the realization of a nonvolatile and SEU-immune flip-flop which is applicable in next-generation CMOS circuits. Simulations of proposed circuits have been performed by SPICE tool and a 45 nm CMOS technology model to evaluate the effectiveness of topologies.

Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

&lt;span&gt;Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes&lt;strong&gt; &lt;/strong&gt;with the lowest transistor&lt;strong&gt; &lt;/strong&gt;count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.&lt;/span&gt;