Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Abstract

For the analysis of the characteristics and behavior of circuits prior to fabrication and to improve circuit performance, simulations using Spice tools are typically performed. Such tools rely on static compact models describing the behavior of the individual circuit components such as transistors. In reality, the behavior of the transistors changes over time due to aging, for instance, as a consequence of bias temperature instabilities (BTI). BTI is typically referred to as a drift of the threshold voltage of a transistor due to charge trapping at oxide and interface defects. To explain BTI, power-law-like mathematical expressions are often employed. However, using these simple formulas, the experimental data can only be replicated with limited accuracy. To evaluate the performance of logic inverter circuits made from 4H-SiC CMOS transistors with high precision, we use a physics-based defect model to describe the change of the device behavior from a defect-centric perspective. Our results indicate the limitations of using power-law-like formulas as they lead to an overly pessimistic estimation for circuit parameters.