Abstract

We investigate bias temperature instability (BTI) charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at a constant oxide electric field for different WFM stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS replacement gate planar transistors with three selected WFM stacks (representative of high-, standard-, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy,” we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75 eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

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