The Involution Tool for Accurate Digital Timing and Power Analysis

Daniel Öhlinger,Jürgen Maier,Matthias Függer,Ulrich Schmid

doi:10.1016/j.vlsi.2020.09.007

Abstract

We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping.We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates.

Highlights

Modern digital circuit design relies heavily on accurate timing analysis tools like Synopsys Prime Time, Mentor Questa, Cadence NC-Sim, or Synopsis VCS
We briefly describe the two simple involution channels currently supported by our tool, namely, exp-channels based on simple exponential switching waveforms, and Hill-channels based on Hill functions that more closely match real switching waveforms. (ii) We demonstrate the utility of the Involution Tool (invTool) by conducting a timing and power analysis of three example circuits: an inverter tree, the clock tree of an open source processor used in the tutorial [12], and a sample circuit that involves multi-input NAND gates, synthetized in two different technologies: 65 nm and 15 nm
To demonstrate the utility of the invTool and to validate/reject some conjectures w.r.t. the existing involution model, we present the results of the evaluation of three different circuits, namely, an inverter tree, where we used a standard 65 nm UMC library (VDD = 1.1 V) that was simulated using SPICE, the clock tree of an open-source MIPS processor [12], and a custom NAND circuit

Summary

INTRODUCTION

Modern digital circuit design relies heavily on accurate timing analysis tools like Synopsys Prime Time, Mentor Questa, Cadence NC-Sim, or Synopsis VCS. The first proper single-history channel model was the Degradation Delay Model (DDM) introduced by Bellido-Dıaz et al [7], [8] It was proven by Fugger et al in [9] that all existing delay models, including DDM, are not faithful: For the simple short-pulse filtration problem, it turned c 2019 IEEE. Main contributions: As, to the best of our knowledge, there is no easy way to apply the involution model to custom signal traces, we developed the Involution Tool (invTool).1 It allows to include and run any IM in state-of-the-art digital circuit simulation tools (e.g. ModelSim), and is embedded in a comprehensive test infrastructure that allows to generate usercontrolled random input vectors, to run different analog/digital simulations, and to generate various reports on the results.

INVOLUTION MODEL

Evaluation

Workflow of the invTool The overall information flow in our tool is shown in

RESULTS

Inverter tree

CONCLUSIONS