SPICE Simulation Research Articles

Relaxation DAC with positive and negative polarity output using high-pass filter

This letter presents a relaxation digital-to-analog converter (ReDAC) configuration with positive and negative polarity output with high pass filter (HPF). Its digital input is provided in two’s complement format, to which the proposed ReDAC configuration directly matches. The configuration and principle are shown and the operation has been verified with SPICE simulation. The proposed ReDAC with HPF is an extension of the conventional ReDAC using low-pass filter (LPF) which generates an analog output with only positive polarity.

New CMOS Linear Transconductors and their Applications

The object of this paper is to introduce a new CMOS differential input single output (DISO) transconductor (realizable from eight MOSFETs operating in saturation) and a dual input dual output (DIDO) transconductor (realizable with 16 MOSFETs operating in saturation) and their applications in realizing grounded/ floating, positive/ negative, electronically controllable resistors and inductors. The workability of all the prepositions has been demostrated by SPICE simulations using TSMC 0.18[Formula: see text] m CMOS technology parameters. The paper, thus, adds a number of useful electronically-controllable circuits to the existing repertoire of CMOS analog circuits for signal processing.

A SPICE-Oriented Method for Finding Multiple DC Solutions in Nonlinear Circuits

Finding multiple operating points of nonlinear circuits is a fundamental issue in electronic circuit analysis and design. Methods that guarantee finding all DC solutions are very time-consuming and can be used to analyze only rather small-sized circuits. On the other hand, there exist approaches that can find multiple operating points, but they do not guarantee finding all solutions. The methods are less time-consuming, do not require much computing power, and allow for analyzing more complex circuits. This paper proposes an efficient method for determining multiple and, in most cases, all DC solutions. The approach uses a deflation technique, and the SPICE simulator is applied to the calculations. For this purpose, the original nonlinear circuit during the computational process was modified appropriately after successive solutions were determined. The method was verified on benchmark nonlinear circuits from the literature, made in various technologies and using various models. The results of the DC analysis of several circuits are provided.

A Design and Validation of 400 W PV Emulator Using Simple Equivalent Circuit for PV Power System Test

In this paper, we propose a photovoltaic emulator (PVE) composed of a series of connected power diodes with a single constant current source, rather than a power converter-based PVE. Accordingly, this enables readily verifying the operation because a the simple hardware structure and lack of a complex control algorithm. The proposed PVE can be intuitively implemented using the proposed selection criteria for the power diode and equivalent resistances. Since there is no feedback control based on complex analog/digital controls and sensors, the control response can be very fast. In addition, the proposed PVE can be easily integrated with a PV power system such as a power optimizer, to allow testing in a simple and flexible manner. Spice simulation was performed based on the electrical characteristics provided by the solar panel manufacturer, and this was utilized to validate the applied emulator circuit model, the Norton Equivalent Circuit. During the design process, the simulation helped to manufacture the PVE within error ranges satisfying the desired I–V and P–V curves, as well as the maximum power point (MPP). Partial shading could be easily implemented through use of the multiple series connection of individual PVEs, demonstrating local MPP and global MPP. A 400 W class PVE was built through appropriate power diode selection, with a thermal design to increase the output power. Moreover, its performance and feasibility were verified through intensive experiments. The measured efficiency, transient response time, and maximum transient error of the partial shading tests were 91%, 22 μs, and 5.8%, respectively.

Modeling of Inrush Current Surges—LED Strip Drivers Case Study

This paper is an investigation into the high inrush current effect that emerges during the energizing of drivers of different circuit types loaded by light-emitting-diode (LED) strips. Two different driver circuit types were analyzed—a voltage stabilization (VS) circuit utilizing a Zener diode, and a current stabilization (CS) circuit type in the form of an integrated circuit (IC). Inrush current waveforms were calculated for drivers loaded by various numbers of LEDs. In the frame of the study, analysis executed for drivers energized by diverse input voltage RMS values at different switching-on phases was performed. The analysis is comprised of experimental verification of LT SPICE simulation results of current waveforms and calculations of current peak values appearing while switching on the supply voltage. The developed models for simulation needs were elaborated concerning precise reflection of the real current and voltage waveforms obtained during oscilloscopic registration of the switching-on process. The assumed simulation model parameters were mainly attuned in view of steady-state current simulations, and the implemented method of high-frequency (HF) transient modeling allowed for precise current waveform reflection. Finally, the utilization effectiveness of the proposed simple inrush current limiting circuit was estimated.

Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators

Recently, resistive RAM (ReRAM)-based hardware accelerators showed unprecedented performance compared the digital accelerators. Technology scaling causes an inevitable increase in interconnect wire resistance, which leads to IR drops that could limit the performance of ReRAM-based accelerators. These IR drops deteriorate the signal integrity and quality, especially in the crossbar structures which are used to build high-density ReRAMs. Hence, finding a software solution, which can predict the effect of IR drop without involving expensive hardware or SPICE simulations, is very desirable. In this article, we propose two neural networks models to predict the impact of the IR drop problem. These models are used to evaluate the performance of the different deep neural network (DNN) models including binary and quantized neural networks showing similar performance (i.e., recognition accuracy) to the golden validation (i.e., SPICE-based DNN validation). In addition, these predication models are incorporated into the DNN training framework to efficiently retrain the DNN models and bridge the accuracy drop. To further enhance the validation accuracy, we propose incremental training methods. The DNN validation results, done through SPICE simulations, show very high improvement in performance close to the baseline performance, which demonstrates the efficacy of the proposed method even with challenging datasets, such as CIFAR10 and SVHN.

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis

With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Aging-aware standard cell library is necessary for robust circuit design. To consider aging effects in standard cell libraries, existing methods mostly require simulating all combinations of aging variables and timing arcs, which are unscalable to large cells. In this brief, we propose an efficient aging-aware standard cell library characterization framework based on sensitivity analysis. We introduce the concept of critical transistors, which can be extracted by sensitivity analysis. By specifying these critical transistors, the number of SPICE simulations can be significantly reduced during the characterization of the aging-aware library. Experimental results on characterizing the standard cells in 16/14nm technology node demonstrate that the proposed method can achieve 1% average relative error and 1.48% maximum relative error with 4.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> to 305 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> speedup, compared with the state-of-the-art work. The method is very flexible and can be deployed into commercial electronic design automation (EDA) tools and libraries.

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.

MOSFET modeling of [formula omitted] CMOS technology at 4.2K using BP neural network

Cryogenic CMOS circuits are widely applied to various fields, such as infrared focal plane arrays, space exploration, and quantum computing. The carrier freeze-out effect at cryogenic temperatures leads to abnormal changes in the characterization of the devices. These cause the performance degradation of circuits or even failure to work. As the industry-standard models provided by manufacturers of CMOS technology cannot describe the cryogenic effects, a complete and precise cryogenic model is required for circuit simulation at cryogenic temperatures. This paper presents the characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at the liquid helium temperature (LHT). To solve the above problem, a metal–oxide–semiconductor field-effect transistor (MOSFET) modeling method at cryogenic temperatures using a back propagation (BP) neural network is proposed. The cryogenic model is first revised based on the BSIM model by extracting physical parameters. Then an optimization model predicted by BP neural network is proposed to calibrate the cryogenic effects. The cryo-model composed of the revised BSIM model and the optimization model can accurately describe the characteristics of MOSFETs with various aspect ratios under different bias voltages at 4.2K, which is not accessible for the standard BSIM model. Meanwhile, the optimization model based on BP neural network has been translated into Verilog-A language to be applied to the SPICE simulator successfully.

IBIS MODEL ACCURACY IMPROVEMENT USING VARIABLE STEP

In all times of integrated circuits (IC) manufacturing, the speed of getting the product on the market has been the main problem for all manufacturers. The main reason for late products has always been the speed of the tools that carry out the testing. The main simulator used by every manufacturer is the SPICE simulator, but with the SPICE simulator it can take up to months to simulate the whole TXRX macro. But since the 1990s with the introduction of the I/O Buffer Information Specification (IBIS) models, the testing time has decreased dramatically. A method is proposed to generate IBIS models with a variable step, that will help to increase the accuracy of the IBIS model during signal integrity (SI) simulations and will correlate with SPICE simulations better. The proposed method can be implemented for all types of TX drivers and IBIS models.

Robust Compact Model of High-Voltage MOSFET’s Drift Region

This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET) devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed to evaluate the delay of CIM operation, power consumption, and analog computational error due to device non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm 2 is improved up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19\times $ </tex-math></inline-formula> . A factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes it highly promising for future edge intelligence.

Fully Binarized, Parallel, RRAM-Based Computing Primitive for In-Memory Similarity Search

In this brief, we propose a fully-binarized XOR-based IMSS (In-Memory Similarity Search) using RRAM (Resistive Random Access Memory) arrays. XOR (Exclusive OR) operation is realized using 2T-2R bitcells arranged along the column in an array. This enables simultaneous match operation across multiple stored data vectors by performing analog column-wise XOR operation and summation to compute HD (Hamming Distance). The proposed scheme is experimentally validated on fabricated RRAM arrays. Full-system validation is performed through SPICE simulations using open source Skywater 130 nm CMOS PDK demonstrating energy of 17 fJ per XOR operation using the proposed bitcell with a full-system power dissipation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$145~\mu \text{W}$ </tex-math></inline-formula> . Using projected estimations at advanced nodes (28 nm) energy savings of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 1.5\times $ </tex-math></inline-formula> compared to the state-of-the-art can be observed for a fixed workload. Application-level validation is performed on HSI (Hyper-Spectral Image) pixel classification task using the Salinas dataset demonstrating an accuracy of 91%.

DESIGN SPACE EXPLORATION OF LOW POWER FULL ADDER ACROSS MULTIPLE LOGIC STYLES AND PROCESS

The signal processing in digital domain becoming ubiquitous, a full adder circuit module has gained prominence for its optimization in terms of its speed, power dissipation, noise margin and area. Further, with the advent of mobile applications on electronic devices, low power has emerged as an overriding design criterion. The proposed work aims to explore the design space of a low power full adder circuit and the implications of logic styles on power-delay trade-offs. Further, the issues impacting the selection of process for design for a given application are addressed. A 1-bit full adder circuit in static CMOS logic style and hybrid logic style is designed and optimized for low-power by carrying out exhaustive simulations using the LT spice simulator in 65 nm and 45 nm standard process to explore their power envelope, before low power process becomes necessary for design. Low power designs are demonstrated and the trade-offs with speed and area are explored.

Pressure sensor diaphragm modelling and deformation analysis

This paper develops Micro-electromechanical Systems-based pressure sensor diaphragms (MEMS). This paper aims to build, model, and test a MEMS-based diaphragm that uses numerous structures of the same area and material to sense differential pressure. Similar goals: Diaphragm deflection and sensitivity were studied using COMSOL multiphysics software. LTspice is a high-performance SPICE simulator with a graphical schematic capture interface. The diaphragm bends when pressure changes, affecting the substrate-diaphragm displacement in COMSOL and the voltage output in LTspice via changing the resistances of three sensors. Voltage output changes with diaphragm bending. Changing voltage and displacement indicate environmental pressure. This method improves instrument response. In this work, a circular diaphragm-based pressure sensor has higher displacement, sensitivity, and stress output responses than a square or rectangular one.

AN ACCURACY IMPROVEMENT TECHNIQUE FOR ON-CHIP CURRENT SOURCES

A new design technique for accuracy improvement of on-chip reference current sources is proposed. A mathematical model has been developed describing the operation of the proposed technique. Based on the obtained equations, the variation of the reference current caused by the changes in operating conditions and process inaccuracies of the technological should not exceed 1…2%. The proposed technique has been implemented in the design of on-chip reference current source circuit in 14 nm FinFet technology. Spice simulations performed for the developed circuit show less than ± 5% variation of the reference current in the -40...1250C temperature range considering the process variations in ±3 sigma range. The circuit keeps that accuracy for the supply voltage drop up to 0.66 V.

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiO&lt;SUB&gt;x&lt;/SUB&gt; Buffer Layer for RRAM Passive Crossbar Array

As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al₂O₃/TiOSUBx/SUB/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOSUBx/SUB encompassing metallic and semiconducting properties; and three devices with different TiOSUBx/SUB were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiOSUB1.74/SUB sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 2SUP7/SUP × 2SUP7/SUP array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL

In this article, we evaluate gate induced drain leakage that affects the refresh time of buried cell array transistor DRAM cells. We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS. In the multi-gate structure, by changing the gate voltage, the work function of the metal gate was adjusted to effectively mitigate the electric field formed in the drain region by approximately four orders. As an adopting multi-gate structure, band to band tunneling is suppressed and gate induced drain leakage current is reduced. We verified that the dual-gate structure had less leakage current than the poly-Si BCAT using the TCAD simulation. The reduction of leakage according to the number of gates is inferred by confirming the reduction in GIDL of the three-gate structure compared with the dual-gate structure. Furthermore, the SPICE simulation confirmed that the proposed select word-line circuit transmits different optimized voltages to multiple gates when it is off than while transferring the same voltage when on. This structure can also be extended for application to other DRAM structures, such as the vertical structure and 3D-stacked DRAMs.

BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation

One of the greatest challenges in integrated circuit design is the repeated executions of computationally expensive SPICE simulations, particularly when highly complex chip testing/verification is involved. Recently, pseudo-transient analysis (PTA) has shown to be one of the most promising continuation SPICE solvers. However, the PTA efficiency is highly influenced by the inserted pseudo-parameters. In this work, we proposed BoA-PTA, a Bayesian optimization accelerated PTA that can substantially accelerate simulations and improve convergence performance without introducing extra errors. Furthermore, our method does not require any pre-computation data or offline training. The acceleration framework can either speed up ongoing, repeated simulations (e.g., Monte-Carlo simulations) immediately or improve new simulations of completely different circuits. BoA-PTA is equipped with cutting-edge machine learning techniques, such as deep learning, Gaussian process, Bayesian optimization, non-stationary monotonic transformation, and variational inference via reparameterization. We assess BoA-PTA in 43 benchmark circuits and real industrial circuits against other SOTA methods and demonstrate an average of 1.5x (maximum 3.5x) for the benchmark circuits and up to 250x speedup for the industrial circuit designs over the original CEPTA without sacrificing any accuracy.

Impedance Coupled Voltage Boosting Circuit for Polyvinylidene Fluoride Based Energy Harvester.

Polyvinylidene fluoride (PVDF) is an emerging method for energy harvesting by fluid motion with superior flexibility. However, the PVDF energy harvester, which has a high internal impedance and generates a low voltage, has a large power transmission loss. To overcome this problem, we propose an impedance-coupled voltage-boosting circuit (IC-VBC) that reduces the impedance of the PVDF energy harvester and boosts the voltage. SPICE simulation results show that IC-VBC reduces the impedance of the PVDF energy harvester from 4.3 MΩ to 320 kΩ and increases the output voltage by 2.52 times. We successfully charged lithium-ion batteries using the PVDF energy harvester and IC-VBC with low-speed wind power generation.