SPICE Simulation Research Articles

SPICE modelling and analysis of hybrid energy harvester combiner topologies

Harvesting energy from multiple hybrid sources and efficiently combining the harvested energies is critical for enabling self-powered devices. Designing an efficient energy combiner is a technical challenge and is non-trivial. Various factors viz. kinds of sources, harvestable energy level and range from the sources, electrical characteristics of sources (low current and high voltage, high current and low voltage, capacitive, inductive etc.), impedance matching (resistive, resistive-reactive, modulus, complex conjugate etc.) of sources, sources scheduling algorithms for combiner, sources switching and control/trigger circuit losses, power conversion and management etc. influence the overall energy combiner’s efficiency. Considering that, this article presents a SPICE modelling and simulation framework for analyzing hybrid energy harvester combiner topologies such as Inductor sharing, voltage level detection and powerORing for its power and energy flow characteristics, regulation, and energy combining efficiency. Such analysis through simulation enables arriving efficient combiner architecture for the chosen harvestable resources, source models, power management circuits and schemes etc. Based on a case study with three different kinds of sources, it has been observed that the voltage level detection technique with DC-DC converters results in the highest efficiency as compared with the other two topologies for such a scenario.

Logical Resolving-Based Methodology for Efficient Reliability Analysis.

With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy.

Jitter due to Random Telegraph Noise: a Study on the Time Dependent Variability of a Ring Oscillator

Random Telegraph Noise is a relevant source of variability in integrated circuits and a growing issue due to device scaling. Jitter is one of its consequences; therefore, it is an important parameter of performance measurements for electronic components and systems. In this paper, the relationship between Random Telegraph Noise and different concepts of jitter is studied. Firstly, a gate delay variability study of a CMOS inverter is discussed. Then, an absolute, a periodic, and a cycle-to-cycle jitter are evaluated in a five-stage ring oscillator. All the data were generated with a spice simulator modified to properly account for Random Telegraph Noise, using the Monte Carlo technique.

Grounded synthetic series lossy inductor simulator circuits employing single current differencing buffered amplifier

SummaryIn this communication, two new positive lossy series inductor simulator circuits using single current differencing buffered amplifier (CDBA), one capacitor, and three resistors are presented. In both the proposed circuits, the inductance value is independently controllable through a grounded resistor, which may be implemented using a voltage‐controlled resistor (VCR), facilitating electronic tuning. Moreover, one of the circuits presented utilizes the intrinsic resistance (internal resistance available at input ports p and n) of the CDBA, thereby enabling electronic control and establishing the inductor simulator as canonical. Both the circuits are analyzed for non‐ideal behavior by taking into account the parasitic elements of CDBA and compared with their ideal counterparts. To demonstrate the efficacy of the proposed series RL simulator circuits, SPICE simulations are performed using CMOS CDBA, and the performance of the proposed circuits is evaluated by designing a lead compensator. The simulation and experimental results of the proposed circuits, along with the application examples employing CDBA realized with the off‐the‐shelf available IC AD844, have also been corroborated.

Machine Learning Based Foreign Object Detection in Wireless Power Transfer Systems

As power electronics continue to drive advancement in electronic devices by managing the system's energy flow, it is advantageous to examine all areas of energy transfer. Wireless power transfer is one section seeing increased adoption in consumer, industrial, and healthcare applications. This consequently increases the concern for safety, reliability, and efficiency. Power transmission to any unintended load is a primary safety issue in high-power wireless power transfer applications, such as unmanned aircraft systems. Foreign object detection is utilized to selectively transmit power to only the intended target to mitigate this issue. This paper seeks to demonstrate a novel alternative method of using machine learning and artificial intelligence techniques for performing foreign object detection solely on the transmitter portion of the system by only monitoring the TX coil current. This method is first evaluated in SPICE simulation software. Then by transitioning to a closed-loop hardware-based testbed designed to be deployed in unmanned aircraft systems. During the test process for the novel FOD method, the aggregate detection accuracy achieved was 83%, including worst-case misalignment conditions with the RX coil. When the outlying worst-case conditions are excluded, the detection accuracy improves to 97%. To measure the FOD effectiveness in preventing temperature rise in a metallic object, the metallic object was placed at the peak power draw location on the transmitter coil. When the metallic object is left at this location for extended periods, the novel FOD method lowers the maximum temperature reached by 86.8°C when compared to no FOD being active. The primary advantage to this novel method is the simplistic hardware additions, which only require minimal alterations to a WPTS without any FOD implemented. Along with this, implementing this foreign object detection method in the transmitter would mitigate the need for a direct communication link between the receiver and transmitter. As a result, the entire system complexity would decrease, thus increasing the UAS power density while maintaining a safe, effective, and reliable wireless power transmission method.

Common-mode noise analysis of silicon microstrip detectors

Silicon microstrip detectors are widely used in space astronomy experiments owing to their high spatial resolution and long-term operational stability. The silicon microstrip detector is affected by bias voltage fluctuations, causing simultaneous changes in the pedestal of all channels under the same power supply. The noise generated by this variation is referred to as common-mode noise (CN). Precisely subtracting the CN can improve the charge resolution of light nuclei. In this study, we investigate the calculation method and sources of CN using the on-orbit data from DAMPE and test beam data of HERD. Our findings confirm that the CN in DAMPE’s silicon microstrip detector primarily arises from fluctuations in the power supply. Furthermore, through the combination of test beam results and SPICE simulations, we have discovered that capacitance-induced charge sharing also contributes to the CN, which increases with the particle charge.

Kernel Mapping Methods of Convolutional Neural Network in 3D NAND Flash Architecture

A flash memory is a non-volatile memory that has a large memory window, high cell density, and reliable switching characteristics and can be used as a synaptic device in a neuromorphic system based on 3D NAND flash architecture. We fabricated a TiN/Al2O3/Si3N4/SiO2/Si stack-based Flash memory device with a polysilicon channel. The input/output signals and output values are binarized for accurate vector-matrix multiplication operations in the hardware. In addition, we propose two kernel mapping methods for convolutional neural networks (CNN) in the neuromorphic system. The VMM operations of two mapping schemes are verified through SPICE simulation. Finally, the off-chip learning in the CNN structure is performed using the Modified National Institute of Standards and Technology (MNIST) dataset. We compared the two schemes in terms of various parameters and determined the advantages and disadvantages of each.

Programmable mixed-signal circuits

A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.

Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extremeenvironment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Special Memristor and Memristor-Based Compact Neuron Circuit

Implementing neuron circuit using memristor can be more effective thanks to some properties of memristor such as nonlinearity. For this reason, many memristor-based neuron circuits have been found in the literature. This study presents a memristor-based floating neuron circuit that exhibits different types of spikes. In the proposed circuit, two classical memristors and one special memristor are utilized. The special memristor is designed to exhibit various pinched hysteresis loops and plays an important role in producing different spike types. The proposed special memristor can also be controlled using only one voltage source. Using memristors, we implemented a neuron circuit which can produce regular spike, bursting spike and fast spike. Also, neuron circuit has a floating structure, and so there is no restriction on using it with other circuit elements. All simulations are implemented in the SPICE simulation program with TSMC 0.18-[Formula: see text]m CMOS process parameters.

Floating parallel lossy inductance, parallel lossy capacitance, parallel C‐D, and lossless capacitance multiplier circuits using current feedback operational amplifiers

SummaryA new synthetic floating simulator topology is proposed which realizes lossy parallel inductance (R‐L), lossy parallel capacitance (R‐C), lossy parallel C‐D, and lossless floating capacitance multiplier (FCM) circuits using only three current feedback operational amplifiers (CFOA) as active elements and three impedances. In all the presented circuits, the value of L, C, and D is independently controllable through a single resistance without requiring any matching condition for passive elements. A novel feature of the proposed circuit involves a straightforward adjustment in the CFOA connections, allowing the circuit to function as either a floating lossless immittance simulator or a floating series‐type lossy immittance simulator. Various application examples of the presented circuits such as lead compensator, lag compensator, first‐order high‐pass filter, and fourth‐order Butterworth filter are also given to justify the theoretical analysis. To validate the workability of the proposed circuits, several analyses are conducted, including frequency analysis, transient analysis, Monte‐Carlo analysis, and temperature analysis, using the macro‐model of AD844 in the SPICE simulation tool. Experimental results of the parallel R‐L simulator and application examples are also provided using commercially available IC AD844‐type integrated CFOAs.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

Two MOS transistor based floating memristor circuit and its application as oscillator

This research article reports a novel off–the-shelf floating memristor circuit based on MOS transistor. The proposed memristor circuit comprises one NMOS, one PMOS and a constant current source. The designed circuit utilized intrinsic parasitic capacitance instead of conventional metal plate capacitor. Pinch hysteresis curve of the designed memristor is maintained for range of frequencies from 380 kHz to 1 GHz. Parameters of the proposed circuit may be tuned by varying the bias current of current source. Performance of the proposed circuit is verified by SPICE simulator using 0.18 µm CMOS technology parameter. In addition, Process corner variation, temperature variation, supply voltage variation and variation in size of transistor are investigated to justify the robustness of the designed circuit. Total power consumption of the designed memristor is 4 µW. Chip area of the proposed circuit is 336.55 µm2. Moreover, applications of the proposed circuit are well described with memristor based Schmitt Trigger circuit and Wien Bridge oscillator circuit.

A tunable and versatile 28 nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses

In this work we report a study and a co-design methodology of an analog SNN crossbar output circuit designed in a 28 nm FD-SOI technology node that comprises a tunable current attenuator and a leak-integrate and fire neurons that would enable the integration of emerging non-volatile memories (eNVMs) for synaptic arrays based on various technologies including phase change (PCRAM), oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories (STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data are used to showcase and estimate the neurons fan-in for each type of eNVM considering the technology constraints and design trade-offs that set its limits such as membrane capacitance, supply voltage, leakage, etc.

Analog circuit sizing based on Evolutionary Algorithms and deep learning

The use of machine learning-based techniques has expanded to many areas that require optimization. One of such area is Integrated Circuit (IC) design and sizing optimization, where we propose a new framework that combines Deep Neural Networks (DNNs) and Evolutionary Algorithm (EA) for analog IC sizing automation. Our optimization framework incorporates EA, numerical performance evaluation, and DNN models to optimize the analog circuit sizing process. The main steps of the proposed optimization procedure can be summarized as follows: Firstly, we use EA and numerical performance evaluation to increase efficiency and produce highly accurate results for global optimization. Secondly, we incorporate a local search to enhance the performance of global optimization, with DNN models being used to evaluate the performance of analog circuits during this phase. Lastly, we employ DNN model evaluations instead of numerical performance evaluation for ranking candidate designs, which significantly speeds up the local minimum search. These successive steps make our method original and stand out perfectly from existing procedures published in the literature. Our framework is deployed on industrial-scale circuits with strict design specifications. Experimental results demonstrate that it achieves better results and is two times faster in the design process compared to traditional global optimization methods that use sequential SPICE simulation calls for local optimization.

Optimal design of BiCMOS second generation current conveyor using the genetic algorithm

This article presents an innovative implementation of the plus-type second-generation current conveyor (CCII+) using BiCMOS technology, which combines the benefits of bipolar and CMOS technologies. The optimization problem of minimizing the X-port input resistance and maximizing the current cut-off frequency value was solved using genetic algorithm (GA). The proposed approach allows the optimization of the BiCMOS CCII+ to achieve better performance compared to previous designs. As a practical application, a second-order band-pass filter using the optimized BiCMOS CCII+ was successfully realized. The performance of the proposed design was evaluated using SPICE simulations and compared with previously published works. This study shows that the BiCMOS CCII+ can be effectively optimized using GA to improve its performance, which has potential applications in various analog and mixed-signal circuits.

Time-domain response of supercapacitors using their impedance parameters and Fourier series decomposition of the excitation signal

Supercapacitors are mostly recognized for their high power density capabilities and fast response time when compared to secondary batteries. However, computing their power in response to a given excitation using the standard formulæof capacitors is misleading and erroneous because supercapacitors are actually non-ideal capacitive devices that cannot be characterized with a single constant capacitance. In this study we show how to estimate accurately the time-domain power and energy of supercapacitors in response to any excitation signal represented in terms of its Fourier series coefficients with the sole knowledge of the frequency-domain impedance parameters of the device. The presented theory is first verified and validated with Spice simulations conducted on an RC network emulating the behavior of a circuit consisting of a resistance (Rs) in series with a constant phase element (CPE) of fractional impedance ZCPE=1/(sCα). Then we do the same for a commercial supercapacitor modeled as an Rs-CPE circuit, and subjected to both a periodic triangular voltage waveform and a random voltage excitation. The results are conclusive and very promising for adopting the proposed procedure to estimate the power and energy performance of supercapacitors in response to real-world charging and discharging signals.

Fast Simulation of Analog Spiking Neural Network With Device Non-Idealites

We present a method for spiking neural network simulation with hardware realistic device non-idealities present in the neuron and synapse circuits as an alternative to time-consumingexpensive spice simulation. Neuromorphic machine learning algorithms for spiking neural networks are often simulatedtested with an ideal mathematical description of spiking neurons and synapses. However, silicon implementations of spiking neurons differ significantly from their ideal mathematical models because of device non-idealities and restrictions in the range of device operation. These non-idealities affect the performance of chip implementations of spiking networks. The dynamical system phase plane of the neuron and synapse circuit is used to create a compact representation of the neuron dynamics that captures device non-idealities for simulation of spiking neural networks. The proposed method would allow hardware-aware optimization of neuromorphic algorithms using standard machine learning tools and provide simulated network prediction close to what would be expected from a chip implementation.

Efficient Wireless Power Transfer Topology for Phone Charging Application

Abstract: Wireless power transfer scheme used on phone chargers are expected to have high efficiency, and reliability. However, existing AC-DC converter schemes were shown to be susceptible to leakage inductance and have lower regulation or excessive power losses. Output voltage regulation is a concern for wireless power converter topologies due to the need for additional shunt devices at DC output. In this paper, literature survey on various wireless power transfer scheme is performed with specific focus on phone charging applications. A modified topology using impedance matching transformer is presented with circuit analysis and LT spice simulation results. It is shown that the proposed topology can deliver better output voltage regulation at various coupling coefficients indicating a superior circuit performance for various separation distances between transmitting and receiving coil.