Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

Abstract

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.