Abstract
With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Aging-aware standard cell library is necessary for robust circuit design. To consider aging effects in standard cell libraries, existing methods mostly require simulating all combinations of aging variables and timing arcs, which are unscalable to large cells. In this brief, we propose an efficient aging-aware standard cell library characterization framework based on sensitivity analysis. We introduce the concept of critical transistors, which can be extracted by sensitivity analysis. By specifying these critical transistors, the number of SPICE simulations can be significantly reduced during the characterization of the aging-aware library. Experimental results on characterizing the standard cells in 16/14nm technology node demonstrate that the proposed method can achieve 1% average relative error and 1.48% maximum relative error with 4.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> to 305 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> speedup, compared with the state-of-the-art work. The method is very flexible and can be deployed into commercial electronic design automation (EDA) tools and libraries.
Published Version
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