Essential Standard Cell Library Composition

Abstract

Current industrial standard cell libraries consist of at least a few hundred to a thousand cells per threshold voltage (VT), and this number keeps increasing with every new process node. These standard cell libraries are composed of a very large set of combinational and sequential logic functions. Generating and maintaining such large libraries is extremely cost intensive. In this paper, we determine the essential standard cell library which is the smallest subset, i.e., comprising the fewest cell functions and fewest drive strengths, of the full standard cell library that can produce power, performance, and area (PPA) results close to that of a full industrial ASIC library for a set of benchmarks. We used a 12nm FinFET-based process node by Global Foundries and an ARM designed standard cell library. State-of-the-art commercial electronic design automation (EDA) tools, Cadence’s Genus and Innovus, were used for logic synthesis and physical synthesis of the benchmark designs, respectively. Our post-routing results show that a standard cell library containing only 14 combinational logic functions and 4 sequential logic functions achieves PPA results with less than 1.7% degradation compared to a full library. This represents a reduction from 838 library cells down to 88, nearly an order of magnitude reduction in library size and its concomitant cost of maintenance. We did not observe any deviation of this conclusion over process corners, nor any dependence on the clock frequency, and there was no observed dependence on the designed chip. Hence, we term this the essential standard cell library since adding any additional cells or sizes to it is unlikely to produce any meaningful reduction in PPA, and whereas reducing any cells or sizes from it appreciably degrades PPA.