Specific On-resistance Research Articles

Design and research of high voltage β-Ga2O3/4H-SiC heterojunction LDMOS

Abstract In recent years, gallium oxide (Ga2O3), one of the ultra-wide band-gap semiconductor materials, has been regarded as one of the most promising materials in the field of high-voltage and high-power electronic devices in the future because of its unique electrical properties and low preparation cost. However, it is difficult for β-Ga2O3 materials to form effective P-type doping, so the PN junction is not formed in most of its power devices, which greatly limits the improvement of its voltage resistance. A novel lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is proposed to realize a junction β-Ga2O3 power device and improve the voltage resistance performance of β-Ga2O3 power devices. In this device, a β-Ga2O3 power device with a junction is realized by using P-type 4H-SiC to form a PN junction with N-type β-Ga2O3, and the voltage resistance of the β-Ga2O3 power device is improved. Sentaurus TCAD software was used to simulate the device structure and electrical performance. The device is optimized by adjusting the length of the drift zone, drift zone concentration, SiC channel concentration, and gate oxide thickness. Optimized, the device exhibits a positive threshold voltage of 3.42 V, a breakdown voltage of 2203 V, a specific on-resistance of 7.80 mΩ·cm2, and a power figure of merit of 622 MW cm−2. The results show that the heterojunction device is significant for realizing high-performance junction β-Ga2O3 power devices.

Design of Ga2O3 Trench Gate MOSFET Devices with Dielectric Pillars

Abstract In this study, a β-Ga2O3 U-groove gate metal-oxide-semiconductor field-effect transistor (UMOSFET) with a high breakdown voltage (BV) is proposed. Through TCAD simulation, both forward and reverse electrical characteristics are comprehensively investigated. The integration of traps within the current blocking layer (CBL) is suggested to enable effective current blocking. Furthermore, to optimize the BV, the introduction of oxide dielectric pillars on either side of the drift layer is implemented to enhance the potential distribution during breakdown. The forward and reverse electrical characteristics of the device at different temperatures are also investigated. Additionally, by conducting simulation optimizations of different doping concentrations in the drift layer, CBL layer thickness, and trap concentrations, notable achievements are realized, which include a high BV of 865.2 V, low threshold voltage of 2.587 V, and low specific ON-resistance of 19.2 mΩ·cm2. This study presents a novel structural design to foster the potential application and development of Ga2O3 electronic devices.

An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer

This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (Ron,sp) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that Ron,sp is reduced by 40.9 % and the FOM (BV2/Ron,sp) is improved by 67.9 % compared to the C-TMBS structure.

Ultra-wide Bandgap AlGaN Channel HEMTs for Portable Power Electronics Applications

AlGaN channel (Eg>3.4 eV) is the most effective method for enhancing the breakdown field of the group III-nitride based HEMTs. This work demonstrates the potential of AlGaN double channel HEMTs on Silicon carbide substrate. The device DC characteristics are investigated using numerical simulator by using drift-diffusion transport model. The AlGaN double channel HEMTs enhances the total 2DEG density due to double potential well and shows better current driving capability (IDS) of 0.714 A/mm, transconductance (gm) of 116 mS/mm, and low specific ON-resistance (Ron) of 3.262 Ω.mm. The AlGaN double channel HEMT on Silicon carbide substrate exhibited 680 V blocking voltage (VBR) and gate field plate HEMT shows 532 V. The effective reduction in electric field at the gate edge is the major source for elevated breakdown voltage in field plate HEMTs. The superior DC characteristics indicates the proposed wide bandgap channel HEMT is suitable device for future portable power converters.

Optimization of Impact Ionization in Metal–Oxide–Semiconductor Field-Effect Transistors for Improvement of Breakdown Voltage and Specific On-Resistance

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

The Minimum Specific On-Resistance of 4H-SiC Superjunction Devices

The Minimum Specific On-Resistance of 4H-SiC Superjunction Devices

Ga2O3 fin field-effect transistors with on-axis (100)-plane gate sidewalls fabricated on Ga2O3 (010) substrates

Ga2O3 fin field-effect transistors (FinFETs) were fabricated on β-Ga2O3 (010) substrates, which had on-axis (100)-plane gate sidewalls treated by nitrogen radical irradiation. The typical FinFET with a fin width (W fin) of 400 nm demonstrated decent on-state device characteristics such as a low specific on-resistance of 6.9 mΩcm2, a high drain current on/off ratio of over 109, and a subthreshold slope of 82 mV/decade. The threshold voltage (V th) of the FinFETs increased with decreasing W fin, and enhancement-mode operation with V th > 0 V was achieved for W fin < 800 nm.

Numerical analysis on the performance enhancement in AlGaN/GaN vertical CAVET with InGaN/AlN/InGaN hybrid current blocking layer

Abstract In this paper, we propose an enhanced superjunction AlGaN/GaN vertical current aperture vertical electron transistor (CAVET) that integrates a novel hybrid InGaN/AlN/InGaN current blocking layer (CBL) situated above the P-column, directly beneath the channel. The incorporation of InGaN substantially elevates the device’s saturation output current by introducing a subchannel beneath the AlGaN/GaN heterojunction conducting channel. Nonetheless, the introduction of AlN engenders a two-dimensional hole gas of opposite polarization direction via the GaN/AlN heterojunction, which aids in depleting the two-dimensional electron gas within the channel, thereby mitigating the issue of negative threshold voltage (V th) bias occasioned by the subchannel introduced by InGaN. The outcomes demonstrate that the maximum saturation output current (I d) for the proposed architecture is 361.5 mA mm−1, with a V th of 1.63 V, marking increases of 98.6% and 0.08% over the traditional superjunction CAVET, respectively. Simultaneously, the breakdown voltage (V br) of the designed device is recorded at 12 064 V, and the specific on-resistance (R on,sp) is 6.45 Ω·mm, showcasing a enhancement figure of merit of 32.9% in comparison to the traditional superjunction CAVET.

High-performance β-Ga2O3 Schottky barrier diodes with Mg current blocking layer using spin-on-glass technique

This study presents a β-Ga2O3 Schottky barrier diode (SBD) with a Mg current blocking layer (Mg-CBL) fabricated via the Mg-doped spin-on-glass (Mg-SOG) technique, affording a surface roughness damage-free thermal doping process. The proposed technique improves the breakdown voltage (BV) of the β-Ga2O3 SBD from 580 to 2200 V and marginally increases the specific on-resistance from 4.0 to 4.8 mΩ cm2, yielding a notable power figure of merit exceeding 1 GW/cm2. The Mg-CBL effectively captures the electrons and mitigates the electric field, leading to a significant increase in BV and slight decrease in the forward current loss. The temperature-dependent I–V curves reveal that the reverse saturation current decreases owing to the physical mechanism of the Mg-CBL structure. Moreover, the Gaussian distribution model is applied to correct the Schottky barrier inhomogeneity stemming from the Mg-CBL. The results illustrate the promising potential of the Mg-CBL fabricated via the Mg-SOG technique for yielding high-performance β-Ga2O3 SBDs.

Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm

The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (Ron,sp) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and Ron,sp is less than the initial Ron,sp. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N+N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and Ron,sp. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.

Gate mesa terminal with drain-field-plated β-Ga2O3 MOSFET with ultra-high power figure of merit

In this article, a novel gate mesa terminal (GMT) device structure incorporating a drain field plate is proposed. This design features mesa terminals with varying bevel angles positioned atop the gate. The objective is to enhance the breakdown voltage (Vbr) and reduce the on-resistance (Ron) of the lateral β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET). Through the implementation of the GMT structure, the peak electric field within the β-Ga2O3 MOSFET is redirected towards the passivation layer. This effectively mitigates the electric field in the epitaxial layer, thereby increasing Vbr. The optimal values for Vbr, specific on-resistance (Ron,sp) and maximum transconductance (gm) across various GMT structures are 4827 V, 9.9 mΩ·cm2 and 15.32 mS/mm, respectively. These metrics represent a 2.63-fold, 0.88-fold, and 1.25-fold improvement compared to the non-GMT structure. Additionally, when the doping concentration of epitaxial layer is 1 × 1016 cm−3, the GMT achieves an enhanced threshold voltage of +0.26 V. By simulating different bevel angles, field plate parameters, epitaxial layer doping concentrations, and mesa thicknesses, an optimal power figure of merit (PFOM) of 1.914 GW cm−2 is attained. This innovative design introduces a fresh concept for the development of the next generation of high voltage and high-power devices rated above 4 KV.

Comparison and analysis on static and dynamic performance of 1.2-kV SiC planar MOSFETs with different cell topologies

1.2-kV SiC MOSFETs with different cell topologies were fabricated based on the same design and process parameters in a commercial 6-inch SiC foundry. A series of comparative evaluations were conducted on the static and dynamic performance of SiC MOSFETs with common linear, island-shaped P+ linear, current sharing linear, and hexagonal cell topologies for the first time. The common linear cell topology has the lowest switching loss, but the highest on-resistance. The island-shaped P+ linear and current sharing linear cell topologies optimized the cell pitch, reduced the specific on-resistance by 9.68 %, but the freewheeling and surge capability of their body diode have been decreased. The current sharing linear cell topology has the highest Ciss/Crss, making it the lowest in crosstalk intensity. The hexagonal cell topology has the lowest on-resistance, but performs the worst in terms of blocking characteristics and switching losses.

1.2 kV SiC MOSFET with Low Specific ON-Resistance and High Immunity to Parasitic Turn-On

With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.

Comparative Performance Evaluation of High-Voltage Bidirectional, Conventional and Superjunction Planar DMOSFETs in 4H-SiC

We quantitively compare the static and dynamic performance for high-voltage SiC bidirectional (BD) conventional and superjunction (SJ) DMOSFETs by using 3D TCAD simulations. We extract the specific on-resistance (RON,sp) and the total specific switching charge (QT,sp), which is a sum of the specific gate charge (QG,sp) and drain charge (QDS,sp) to quantify both the static and switching characteristics respectively. We also develop a new Figure-of-Merit (FoM), which is the product of RON,sp . QT,sp, to evaluate the overall performance. We show that the high-voltage 4H-SiC BD SJ DMOSFET has the best FoM with substantial (&gt;58%) improvement, compared to the BD conventional DMOSFETs, which increases with increasing breakdown voltage.

Design and evaluation of β-Ga2O3 junction barrier schottky diode with p-GaN heterojunction

A novel design for a junction barrier Schottky (JBS) diode based on a p-GaN/n-Ga2O3 heterojunction is proposed, exhibiting superior static characteristics and a higher breakdown capability compared to the traditional Ga2O3 Schottky barrier diode (SBD). By utilizing wide-bandgap p-type GaN, the β-Ga2O3 JBS diodes demonstrate a turn-on voltage (V on ) of approximately 0.8 V. Moreover, a breakdown voltage (V br ) of 880 V and a specific on-resistance (R on,sp ) of 3.96 mΩ·cm2 are achieved, resulting in a Baliga’s figure of merit (BFOM) of approximately 0.2 GW /cm 2. A forward current density of 465 A cm−2 at a forward voltage of 3 V is attained. The simulated reverse leakage current density remains low at 9.0 mA cm−2 at 800 V. Floating field rings, in conjunction with junction termination extension (JTE), were utilized as edge termination methods to attain a high breakdown voltage. The impact of β-Ga2O3 periodic fin width fluctuations on the electrical characteristics of JBS was investigated. Due to the enhanced sidewall depletion effect caused by p-type GaN, the forward current (I F ) and reverse current (I R ) decrease when the β-Ga2O3 periodic fin width decreases. The findings of this study indicate the remarkable promise of p-GaN/n-Ga2O3 JBS diodes for power device applications.

(Electronics and Photonics Division Poster Award Winner) A High Breakdown Voltage Silicon Carbide (SiC)/Gallium Oxide (Ga2O3) Heterojunction Diode for High Power Applications

Wide and ultrawide bandgap semiconductors demonstrate exceptional performance due to their elevated energy bandgap. This characteristic results in breakdown electric fields surpassing those found in conventional silicon electronics by more than an order of magnitude. Furthermore, the high energy bandgap offers distinctive advantages, including enhanced efficiency, drift velocity, increased voltage blocking, and high-frequency switching, making these semiconductors crucial in pushing the boundaries of electronic technology. Gallium Oxide and Silicon Carbide, distinguished by their unique properties, contribute significantly to the advancement of power electronics. Gallium Oxide, with its wide bandgap of 4.6 – 4.9 eV and excellent thermal stability, stands out for its ability to handle high electric fields and temperatures. Silicon Carbide, on the other hand, boasts a robust combination of high thermal conductivity and a wide bandgap of 3.26 eV, making it well-suited for high-power and high-temperature applications. The combination of these two materials in a heterojunction holds promise for the development of high-performance power devices. In this study, we propose a novel high breakdown voltage Silicon Carbide (SiC)/ Gallium Oxide(Ga2O3) heterojunction diode through TCAD Sentaurus. We present a comparative study of the breakdown voltage and electric field across different heterojunction lengths and under various doping concentrations. The investigated heterojunction showcases a high breakdown voltage of 1899V, making it a promising candidate for advanced power electronics applications. Furthermore, simulation results revealed a significant increase in the breakdown voltage of the SiC/Ga2O3 heterojunction, escalating from 1899 V to 4864 V when extending the heterojunction length. Improved specific ON resistance (RON, sp) and Baliga figure-of-merit (BFOM) will also be presented.

A normally off high-voltage InGaZnO transistor with drain offset region modulated by an InZnO layer

This work presents a normally off high-voltage indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) featuring a drain offset region modulated by the IZO layer (IMO, IMO-IGZO TFT). In addition to decreasing the specific on-resistance (Ron,sp) by more than three orders of magnitude, the IMO structure further elevates the breakdown voltage by optimizing the thickness of the IZO layer (tIZO) compared to the Offset TFT. Through TCAD simulation, the underlying mechanism responsible for the improved performance of the IMO-IGZO TFT is elucidated. The introduced IZO modulating layer effectively increases carrier concentration and rebuilds the electric field within the offset region. Consequently, the IMO-IGZO TFT with a 6 nm thick IZO modulating layer and 3.5 μm length offset region attains a breakdown voltage of 410 V and demonstrates favorable Ron,sp of 5.3 × 103 mΩ × cm2. This results in a Baliga's figure of merit of 31.72 kW/cm2, surpassing conventional and Offset TFTs by factors of 186 and 3048, respectively.

Barrier height enhancement in β-Ga2O3 Schottky diodes using an oxygen-rich ultra-thin AlOx interfacial layer

Schottky barrier height (SBH) enhancement directly translates into increased breakdown voltage (VBR) of β-Ga2O3 Schottky barrier diodes (SBDs). In this work, ultra-thin (5, 10, and 15 Å) oxygen-rich AlOx interfacial layers (ILs), deposited using plasma-enhanced atomic layer deposition, are shown to enhance the SBH of post-metallization oxygen annealed Pt/AlOx/β-Ga2O3 SBDs by up to 0.8 eV resulting in a maximum VBR of nearly 500 V (2× gain) on 2–4 × 1016 cm−3 doped substrates, without compromising the specific on-resistance. The SBH and VBR enhancement is observed on (2¯ 01) as well as (001) surfaces. X-ray photoelectron spectroscopy (XPS) analysis shows that excess oxygen interstitial concentration in 5 Å AlOx films decreases (increases) with increasing thickness (oxygen anneal), making them more stoichiometric. The decreasing (increasing) trend in SBH and VBR with increasing IL thickness (oxygen anneal) is consistent with the XPS-derived O/Al ratio of the films and the formation of an AlOx/β-Ga2O3 interfacial dipole due to a difference in oxygen areal densities. The AlOx deposition can be easily integrated with field management methods such as field plates and guard rings that can further enhance β-Ga2O3 SBD performance.

Electrical properties of unintentionally doped β-Ga2O3 (010) thin films grown by a low-pressure hot-wall metalorganic chemical vapor deposition

We investigated the electrical properties of unintentionally doped (UID) Ga2O3 (010) layers grown by low-pressure hot-wall metalorganic chemical vapor depositions from device characteristics of Schottky barrier diodes (SBDs) fabricated on them. Highly resistive properties of the UID Ga2O3 layers were confirmed from current–voltage characteristics. The specific on-resistance of the SBD with the most resistive UID Ga2O3 layer was 2.2 × 107 Ωcm2. Capacitance–voltage characteristics revealed that most of the SBDs had complete depletion of the UID layers at thermal equilibrium, indicating that their residual effective donor densities were less than 3.0 × 1013 cm−3.