Specific On-resistance Research Articles

Effect of hydrogen treatment on 4H-SiC Schottky barrier diodes

In this letter, 4H-SiC Schottky barrier diodes (SBDs) with Ti Schottky metal have been subjected to hydrogen treatment in a confined environment of 4% H2 and 96% N2 at 150 °C. The effect of hydrogen treatment on the SBDs electrical characteristics has been investigated by technical computer-aided design simulation (TCAD) and power device analyzer curve tracer. The change of electrical parameters of SBDs measured after hydrogen treatment is studied in detail, and the related degradation mechanism is discussed. It was found that hydrogen treatment affected both the interface region and bulk region of SiC SBDs. After hydrogen treatment, the Schottky barrier increases slightly, the ideal factor (n) decreases slightly, and the interfacial state density (D it) decreases. Hydrogen treatment resulted in a slight reduction in specific on-resistance (R on-sp), which was attributed to the diffusion of H in SBDs. Through TCAD simulation, it is determined that the diffusion of H in the body diode of SBDs is the main reason for the degradation of high forward current and high reverse voltage characteristics.

Breakdown voltage enhancement and specific on-resistance reduction in depletion-mode GaN HEMTs by co-modulating electric field

In this letter, a depletion-mode GaN high electron mobility transistors (GaN HEMTs) with high breakdown voltage and low on-resistance are designed and experimentally demonstrated. It combines the gate field plate and partial unintentionally doped GaN (u-GaN) cap layer (gate field plate and partial u-GaN cap HEMTs: GPU-HEMTs) to co-modulate the surface electric field distribution, which results in the electric field peak being far away from the gate edge, thus improving the breakdown voltage and decreasing the on-resistance. The optimized GPU-HEMTs exhibit a larger output current (I DS) of 495 mA mm−1 and a correspondingly smaller specific on-resistance of 4.26 mΩ·cm2. Meanwhile, a high breakdown voltage of 1044 V at I DS = 1 mA mm−1 compared to the conventional GaN HEMTs of 633 V was obtained. This approach is highly effective in simultaneously optimizing the breakdown voltage and the specific on-resistance of GaN HEMTs, while maintaining a large output current.

Analytical modeling of threshold voltage and on-resistance in multi-barrier E-mode MISHEMT with gate-recess and field-plates

This work presents an analytical model for threshold voltage and On-resistance of multi barrier Metal–Insulator–Semiconductor High-Electron-Mobility-Transistor (MISHEMT) with gate-recess and field-plates. The device featuring a high two-dimensional electron-gas (2DEG) density in the channel region. The primary objectives of this device are to achieve a high threshold voltage (Vth) and enhance electron mobility with specific low ON-resistance (Ron_sp) by mitigating the degradation effects arising from scattering and interface-charges. Also, a physics based analytical model for Vth and 2DEG charge density at upper and lower channels is presented. This model is validated by comparing with TCAD numerical simulations and are well matched. The proposed MISHEMT demonstrates improved electron mobility in the lower channel of 1260 cm2/V.s, Vth of ∼2.6 V and Ron_sp is minimized by 33 % in contrast with a conventional MISHEMT. Additionally, the proposed MISHEMT becomes a promising device for achieving both high threshold voltage and mobility which are required for power semiconductor devices.

A semi-cellular Z-type Gate SOI-LDMOS with Improved Gate Control Capability

A Semi-cellular Z-type Gate SOI-LDMOS (ZG LDMOS) with Improved Gate Control Capability is proposed, and its physical mechanism is studied by SENTAURUS. It is a semi-cellular structure similar to "Z" consisting of a Trench Gate (TG) and a Planar Gate (PG). At the on-state, the inversion layer of the conductive channel is not only formed at the top of the P-well region, but also formed along the side wall of the Z Gate, expanding the width of the channel, improving the electron injection ability and reducing the specific on-resistance (Ron,sp). In addition, the Z Gate can also form a uniform current distribution from the drift region to the bottom, which is helpful to reduce the Ron,sp, improve the transconductance and enhance the current control ability. The 3D simulation results show that BV, Ron,sp are 187.3 V and 4.45 mΩ cm2, respectively. The FOM reached 7.91 MW/cm2. Compared with the conventional LDMOS, the FOM value of ZG LDMOS increased by 58.8 %, which breaks through the silicon limit of RESURF.

Study on a p-GaN HEMT with composite passivation and composite barrier layers

A novel structure of p-GaN high-electron-mobility transistor (HEMT) is proposed and studied. It features two composite layers. One is the composite passivation (CP) layer consisting of Si3N4 and high-permittivity (HK) film. The other is a composite barrier (CB) layer consisting of Al x Ga1−x N/AlN/Al0.23Ga0.77N. Due to the coordinated effect of CP and CB, the specific on-resistance (R ON, SP) can be reduced under the premise of ensuring breakdown voltage (BV). Meanwhile, since the HK film in CP introduces a mechanism to automatically compensate the hot electrons trapped by surface states, the current collapse effect could be suppressed. According to the simulation results, in comparison with the conventional p-GaN HEMT, the proposed one using TiO2 as the HK material and using Al-component of 0.35 for Al x Ga1−x N gains a 29.5% reduction in R ON, SP while getting a 9.8% increase in BV, which contributes to a 50.5% decrease in the energy loss during one cycle at 200 kHz. It is also demonstrated by the simulation results that the current collapse in the proposed device is reduced by 28.6%. Thereby, a promising p-GaN HEMT with improved performance and reliability is invented.

Electrical performance and reliability analysis of vertical gallium nitride Schottky barrier diodes with dual-ion implanted edge termination

In this study, a gallium nitride (GaN) substrate and its 15 μm epitaxial layer were entirely grown using hydride vapor phase epitaxy (HVPE). To enhance the breakdown voltage (VBR) of vertical GaN-on-GaN Schottky Barrier Diodes (SBDs), a dual ion co-implantation of carbon and helium was used to create the edge termination. The resulting devices exhibited low turn-on voltage of 0.55 V, high Ion/Ioff of approximately 109, and low specific on-resistance of 1.93 mΩ·cm2. With the ion implantation edge termination, the devices achieved a maximum VBR of 1575 V, with an average improvement of 126%. These devices demonstrated a high figure of merit (FOM) of 1.28 GW/cm2 and showed excellent reliability during pulse stress testing.

18 A/1020 V p-GaN-gated HEMTs with Isosceles Trapezoidal-Shaped Multi-Finger Structure

In this article, we investigate the effects of gate and drain field plates and isosceles trapezoidal-shaped multi-finger structures on the characteristics of high current p-GaN-gated high-electron-mobility transistors (HEMTs). By optimizing the lengths of gate and drain field plates, the p-GaN-gated HEMTs with 200 μm have a breakdown voltage of 1893 V, a specific on-resistance of 7.0 mΩ-cm2, and a Baliga figure of merit (BFOM) value of 511 MW cm−2. Using the optimized isosceles trapezoidal-shaped multi-finger metallization on the source and drain, the p-GaN-gated HEMT with a 100 mm gate width can reach a current of 2.3 A. Combining all the optimum parameters of field plates and isosceles trapezoidal-shaped multi-finger, the fabricated 600 mm p-GaN-gated HEMT exhibits an output current of 18 A, an on-resistance of 0.7 Ω, and a breakdown voltage of 1020 V. Furthermore, the device also exhibits good thermal stability at high temperatures. These results demonstrate the potential and advantages of p-GaN-gated HEMT for power applications.

Novel superjunction Fin-based NiO/β-Ga2O3 HJFET with additional surface drift region channels for record-high performance

—In this paper, a novel superjunction fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (SJ Fin-HJFET) is proposed and studied by simulations. Compared with the conventional Ga2O3 SJ FinFET, Ga2O3 SJ Fin-HJFET can generate surface conduction channels instead of depletion zones near the p-n junction interface in the SJ drift region. The additional surface conduction channel significantly improves the specific on-resistance of the SJ Fin-HJFET (from 1.091 mΩ cm2 to 0.397 mΩ cm2, reduced by 63.6 %) and dramatically improves the Baliga figure of merit (BFOM, form 11.75 GW/cm2 to 32.28 GW/cm2) at the same breakdown voltage (3580 V). The effect of different conduction band offset (ΔEC) on the performance of the SJ Fin-HJFET is also investigated. The simulation results show that the on-resistance advantage of the SJ Fin-HJFET applies to a wide range of ΔEC, exhibiting strong applicability and stability. These results indicate that the SJ Fin-HJFET has record-high performance and promising application prospects.

High growth rate metal organic chemical vapor deposition grown Ga2O3 (010) Schottky diodes

We report on the growth of Si-doped homoepitaxial β-Ga2O3 thin films on (010) Ga2O3 substrates via metal-organic chemical vapor deposition (MOCVD) utilizing triethylgallium (TEGa) and trimethylgallium (TMGa) precursors. The epitaxial growth achieved an impressive 9.5 μm thickness at 3 μm/h using TMGa, a significant advance in material growth for electronic device fabrication. This paper systematically studies the Schottky barrier diodes fabricated on the three MOCVD-grown films, each exhibiting variations in the epilayer thickness, doping levels, and growth rates. The diode from the 2 μm thick Ga2O3 epilayer with TEGa precursor demonstrates promising forward current densities, the lowest specific on-resistance, and the lowest ideality factor, endorsing TEGa’s potential for MOCVD growth. Conversely, the diode from the 9.5 μm thick Ga2O3 layer with TMGa precursor exhibits excellent characteristics in terms of lowest leakage current, highest on-off ratio, and highest reverse breakdown voltage of −510 V without any electric field management, emphasizing TMGa’s suitability for achieving high growth rates in Ga2O3 epilayers for vertical power electronic devices.

Enhancement of Electrical Safe Operation Area of 60 V nLDMOS by Engineering of Reduced Surface Electrical Field in the Drift Region.

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 1012 cm-2 can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BVon). In addition, the extended n-drift region length of the Ld design also improves device BVon significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BVon performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BVoff) of 88.4 V and the specific ON-resistance (RON,sp) of 129.7 mΩ⋅mm2 exhibit only a slight sacrifice.

Analysis and simulation of bulk polarization mechanism in p-GaN HEMT with AI component gradient buffer layer

In this paper,bulk polarization mechanism and radiation simulation of the Al component gradient buffer layer (GBL) and constant buffer layer (CBL) of p-GaN HEMT (p-GaN GBL-HEMT and p-GaN CBL-HEMT) are analyzed and studied. It is found that the p-GaN GBL-HEMT can significantly reduce the buffer leakage current. The linear gradient amplitude (the range of linear gradients of Al components vertically in the buffer) of 20%–25% Al components can significantly increase the breakdown voltage (V BK) of the device, up to 1312 V. Simultaneously, although the p-GaN GBL-HEMT reduces the 2DEG concentration, the device still has a specific on-resistance (R ON,sp) and drain saturation current (I DS,sat) equivalent to the p-GaN CBL-HEMT due to the conductivity modulation effect. Its Baliga figure of merit is up to 2.27 GW cm−2. Finally, through the SEE simulation and the bulk polarization mechanism analysis, it is found that the drain transient current (I DS,trans) by the identical incident particles in the p-GaN GBL-HEMT is lower than that in the p-GaN CBL-HEMT, and the I DS,trans decreases with the increase of the Al components gradient amplitude. Therefore, the p-GaN GBL-HEMT provides a new idea for improving the electrical performance and SEE hardening.

3.3 kV-class NiO/β-Ga2O3 heterojunction diode and its off-state leakage mechanism

This Letter demonstrates a high-performance 3.3 kV-class β-Ga2O3 vertical heterojunction diode (HJD) along with an investigation into its off-state leakage mechanism. The vertical β-Ga2O3 HJD with field plate assisted deep mesa (FPDM) termination was fabricated using a self-aligned technique to etch the deep mesa to a depth of 9 μm, thereby reducing electric field crowding at the anode edge. In addition, a thick dielectric is deposited to fill the trench, facilitating the utilization of a field plate to further reduce the electric field at the anode edge. TCAD (Technology Computer Aided Design) simulations show significant suppression of electric field crowding at the anode edge. The fabricated HJD exhibits a high current swing of ∼1010 over a temperature range from 25 °C to 175 °C. The specific on-resistance (Ron,sp) is extracted to be 3.9 mΩ cm2, and the breakdown voltage is 3.42 kV with the FPDM termination. These conduction and blocking characteristics lead to a high power figure of merit of 3 GW/cm2, which is one of the highest among multi-kilovolt β-Ga2O3 diodes. Furthermore, the off-state current leakage mechanism of the HJD under a reverse bias up to 2000 V was investigated. The fitted results reveal that the leakage current is primarily dominated by Poole–Frenkel (PF) emission, with the trap level of PF extracted to be 0.36 eV below the conduction band of NiO.

A 1.6 kV Ga2O3 Schottky Barrier Diode with a Low Reverse Current of 1.2 × 10-5 A/cm2 Enabled by Field Plates and N Ion-Implantation Edge Termination.

In this work, by employing field plate (FP) and N ion-implantation edge termination (NIET) structure, the electrical performance of the β-Ga2O3 Schottky barrier diode (SBD) was greatly improved. Ten samples of vertical SBDs were fabricated to investigate the influence of the relative positions of field plates (FPs) and ion implantation on the device performance. The device with the FP of 15 μm and the ion implantation at the edge of the Schottky electrode exhibited a breakdown voltage (Vbr) of 1616 V, a specific on-resistance (Ron,sp) of 5.11 mΩ·cm2, a power figure of merit (PFOM) of 0.511 GW/cm2, and a reverse current density of 1.2 × 10-5 A/cm2 @ -1000 V. Compared to the control device, although the Ron,sp increased by 1 mΩ·cm2, the Vbr of the device increased by 183% and the PFOM increased by 546.8%. Moreover, the reverse leakage current of the device with the FP and NIET structure decreased by three orders of magnitude. The TCAD simulation revealed that the peak electric field at the interface decreased from 7 MV/cm @ -500 V to 4.18 MV/cm @ -1000 V. These results demonstrate the great potential for the β-Ga2O3 SBD with a FP and NIET structure in power electronic applications.

Enhanced Theoretical Lower Limit for the Specific On-Resistance of a Silicon Balanced Superjunction

Enhanced Theoretical Lower Limit for the Specific On-Resistance of a Silicon Balanced Superjunction

A Novel 4H-SiC Asymmetric MOSFET with Step Trench.

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (Ron,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (RJFET) and the electric field in the gate oxide (Eox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs.

A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

In this paper, a novel double-gate trench silicon-on-insulator lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (R on,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS, when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the R on,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/R on,sp) is increased by 397.2% from 3.6 MW cm−2 to 17.9 MW cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

Low turn-on voltage and 2.3 kV β -Ga2O3 heterojunction barrier Schottky diodes with Mo anode

In this work, we propose combining a low work function anode metal and junction barrier Schottky structure to simultaneously achieve low turn-on voltage (Von) and high breakdown voltage (BV), which alleviates the dilemma that high BV requires high Schottky barrier height (SBH) and high Von. Molybdenum (Mo) is used to serve as the anode metal to reduce the SBH and facilitate fast turn-on to achieve a low Von. To resolve the low SBH related low BV issue, a p-NiO/n-Ga2O3-based heterojunction structure is used to enhance β-Ga2O3 sidewall depletion during the reverse state to improve the BV. With such a design, a low Von = 0.64 V(@1A/cm2) and a high BV = 2.34 kV as well as a specific on-resistance (Ron,sp) of 5.3 mΩ cm2 are demonstrated on a 10 μm-drift layer with a doping concentration of 1.5 × 1016 cm−3. β-Ga2O3 JBS diodes with low Von = 0.64 V and a power figure of merit of 1.03 GW/cm2 show great potential for future high-voltage and high-efficiency power electronics.